Day 10

Design and verify a counter which supports loading a value and restarting from the last loaded value when the counter rolls-over. This is commonly known as a self-reloading counter.

Interface Definition

• Counter should reset to 0
• The module should have the following interface:

input     wire          clk,
input     wire          reset,
input     wire          load_i,     -> Load value is valid this cycle
input     wire[3:0]     load_val_i, -> 4-bit load value

output    wire[3:0]     count_o     -> Counter output

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing the checks or the testbench code then I'd recommend the Hands-on RTL Design course. The course contains 25 RTL Design problems to help improve your design skills and comes with a 2-part video solution for every problem.