Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 12
Design and verify a sequence detector to detect the following sequence:
`1110_1101_1011`

## Interface Definition
- Overlapping sequences should be detected
- The module should have the following interface:

```verilog
input     wire        clk,
input     wire        reset,
input     wire        x_i,    -> Serial input

output    wire        det_o   -> Output asserted when sequence is detected
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing
the checks or the testbench code then I'd recommend the [Hands-on RTL Design](https://quicksilicon.in/course/rtl-design/?utm_source=quicksilicon&utm_medium=21DaysofRT&utm_campaign=cross-link) course.
The course contains 25 RTL Design problems to help improve your design skills and comes with a
2-part video solution for every problem.

## Challenge
Try solving [this](https://quicksilicon.in/course/rtl-design/module/sequence-generator) problem which deals with designing a sequence generator!


## RTL
```verilog
// Detecting a big sequence - 1110_1101_1011
module day12 (
  input     wire        clk,
  input     wire        reset,
  input     wire        x_i,

  output    wire        det_o
);

  // Use a shift register to sample the serial input
  logic[11:0] shift_ff;
  logic[11:0] nxt_shift;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      shift_ff <= 12'h0;
    else
      shift_ff <= nxt_shift;

  assign nxt_shift = {shift_ff[10:0], x_i};

  assign det_o = (shift_ff[11:0] == 12'b1110_1101_1011);

endmodule
```
## TB
```verilog
module day12_tb ();

  logic         clk;
  logic         reset;
  logic         x_i;
  logic         det_o;

  day12 DAY12 (.*);

  always begin
    clk = 1'b1;
    #5;
    clk = 1'b0;
    #5;
  end

  logic [11:0] seq = 12'b1110_1101_1011;

  initial begin
    reset <= 1'b1;
    x_i <= 1'b1;
    @(posedge clk);
    reset <= 1'b0;
    @(posedge clk);
    for (int i=0; i<12; i=i+1) begin
      x_i <= seq[i];
      @(posedge clk);
    end
    for (int i=0; i<12; i=i+1) begin
      x_i <= $random%2;
      @(posedge clk);
    end
    $finish();
  end

endmodule
```
