Day 12

Design and verify a sequence detector to detect the following sequence: 1110_1101_1011

Interface Definition

• Overlapping sequences should be detected
• The module should have the following interface:

input     wire        clk,
input     wire        reset,
input     wire        x_i,    -> Serial input

output    wire        det_o   -> Output asserted when sequence is detected

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing the checks or the testbench code then I'd recommend the Hands-on RTL Design course. The course contains 25 RTL Design problems to help improve your design skills and comes with a 2-part video solution for every problem.

Challenge

Try solving this problem which deals with designing a sequence generator!