Day 15

Design and verify a 4-bit round robin arbiter.

Interface Definition

Output should be produced in a single cycle
Output must be one-hot
The module should have the following interface:

module day15 (
  input     wire        clk,
  input     wire        reset,

  input     wire[3:0]   req_i,
  output    logic[3:0]  gnt_o
);

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

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Challenge

Design a parameterized round-robin arbiter

initializing...