Day 3

Design and verify a rising and falling edge detector

Interface Definition

The module should have the following interface:

input     wire    clk,
input     wire    reset,

input     wire    a_i,            -> Serial input to the module

output    wire    rising_edge_o,  -> Rising edge output
output    wire    falling_edge_o  -> Falling edge output

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing the checks or the testbench code then I'd recommend the Hands-on RTL Design course. The course contains 25 RTL Design problems to help improve your design skills and comes with a 2-part video solution for every problem.