Day 4

Design and verify a 8-bit ALU which supports the following encoded operations:

Encoding	Operation	Comment
3'b000	ADD	-
3'b001	SUB	-
3'b010	SLL	Vector a should left shift using bits 2:0 of vector b
3'b011	LSR	Vector a should right shift using bits 2:0 of vector b
3'b100	AND	-
3'b101	OR	-
3'b110	XOR	-
3'b111	EQL	Output should be 1 when equal otherwise 0

Interface Definition

The module should have the following interface:

input     logic [7:0]   a_i,  - First 8-bit input vector
input     logic [7:0]   b_i,  - Second 8-bit input vector
input     logic [2:0]   op_i, - Encoded operation

output    logic [7:0]   alu_o - ALU output

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing the checks or the testbench code then I'd recommend the Hands-on RTL Design course. The course contains 25 RTL Design problems to help improve your design skills and comes with a 2-part video solution for every problem.

Challenge

Try solving this problem which deals with designing the ALU for a RISC-V Processor.

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initializing...