Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Alice wants to design a circuit which takes two serial inputs `sig_x_i` and `sig_y_i`
such that the input `sig_y_i` has randomly delayed versions of `1s` seen on the input
`sig_x_i`. The circuit produces an output `z_o` which is asserted whenever there is
an expectation of seeing a `1` on the `sig_y_i` input.
Alice needs your help in designing the circuit.



Cross Correlation