1
Edge Capture
NOT SUBMITTED
Quite often your logic needs to react to a change on some control signal. That can be an external input, something saying that another part of the circuit has done it's job and that it is safe to continue. All sorts of scenarios exist that call for a signal generated by one part of a system to be detected by another part or a different system.
Implement a sticky edge detector (or a edge capture) circuit which captures any neg-edge (from 1-0) transition on a 32-bit input signal.
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Sublime
Emacs
Sublime
Vim
System Verilog
Verilog
VHDL
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY