VIPT Cache Top

This lesson would cover the microarchitecture and RTL design of the instruction tag pipeline. As a quick recap, the Virtually Indexed and Physically Tagged cache has the following parameters:

• Size: 4KB
• Number of ways: 4
• Cacheline size: 4B (32b)
• Number of sets: 256
• Page size granularity: 4KB

The tag pipeline is one of the crucial building block of the instruction cache since it stores the PA (the tag) and gives us the hit information. The tag RAMs are also arranged on per way basis to allow reading the tag stored in each of the ways of the set. The read tag is then compared across the ways with the current PA being accessed to find the hit way. Once the hit way is known it can be used to mux-out the data from the data RAMs as it would be seen in the upcoming lessons. However, if none of the ways contain a valid tag or match with the current PA, a miss request is sent to get the data and the processor stalls until it is available.

The tag pipeline is hence responsible for all of the above discussed functions which include:

• Looking up the instruction Tag RAMs
• Tracking the valid array for each set and way of the cache
• Implementing the cache replacement policy on a miss
• Logic to stall the processor on a miss and send out the miss requests

Let's take a deeper look at each of these functions before we start designing the tag pipeline.