Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 21
Design and verify a module which finds the second bit set from LSB for a N-bit vector.

## Interface Definition
- Output should be produced in a single cycle
- Output must be one-hot or zero
- The module should have the following interface:

```verilog
module day21 #(
  parameter WIDTH = 12
)(
    input  wire [WIDTH-1:0] vec_i,
    output wire [WIDTH-1:0] second_bit_o
);
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

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## RTL
```verilog
module day21 #(
  parameter WIDTH = 12
)(
  input       wire [WIDTH-1:0]  vec_i,
  output      wire [WIDTH-1:0]  second_bit_o

);

  logic [WIDTH-1:0] first_bit;
  logic [WIDTH-1:0] masked_vec;

  // Find the first bit set
  day14 #(.NUM_PORTS(WIDTH)) find_first (
    .req_i          (vec_i),
    .gnt_o          (first_bit)
  );

  // Mask the first bit
  assign masked_vec = vec_i & ~first_bit;

  // Do a find first set on the masked vector to get second bit set
  day14 #(.NUM_PORTS(WIDTH)) find_second (
    .req_i          (masked_vec),
    .gnt_o          (second_bit_o)
  );

endmodule

module day14 #(
  parameter NUM_PORTS = 4
)(
    input       wire[NUM_PORTS-1:0] req_i,
    output      wire[NUM_PORTS-1:0] gnt_o   // One-hot grant signal
);
  // Port[0] has highest priority
  assign gnt_o[0] = req_i[0];

  genvar i;
  for (i=1; i<NUM_PORTS; i=i+1) begin
    assign gnt_o[i] = req_i[i] & ~(|gnt_o[i-1:0]);
  end

endmodule
```

## TB
```verilog
module day21_tb ();

  localparam WIDTH = 16;

  logic[WIDTH-1:0] vec_i;
  logic[WIDTH-1:0] second_bit_o;

  day21 #(WIDTH) DAY21 (.*);

  initial begin
    for (int i=0; i<64; i=i+1) begin
      vec_i = $urandom_range(0, 2**WIDTH-1);
      #5;
    end
  end

endmodule
```
