21 Days of RTLCourse

Pick up where you left off and continue mastering production-ready RTL design techniques.

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Course Modules

Master SystemVerilog through 22 carefully crafted modules designed to build your skills progressively.

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Showing 22 of 22 modules

Day 1

EASY

Mux

Day 2

EASY

D Flip-Flop

Day 3

EASY

Edge Detector

Day 4

EASY

Simple ALU

Day 5

EASY

Odd counter

Day 6

EASY

Shift register

Day 7

EASY

LFSR

Day 8

EASY

Binary to One-hot

Day 9

EASY

Binary to Grey

Day 10

EASY

Self reloading counter

Day 11

EASY

Parallel to Serial

Day 12

EASY

Sequence Detector

Day 13

EASY

Muxes

Day 14

EASY

Fixed Priority Arbitrer

Day 15

EASY

Rround Robin Arbitrer

Day 16

EASY

APB Master

Day 17

EASY

Simple Memory Interface

Day 18

EASY

APB Slave

Day 19

EASY

Synchronous Fifo

Day 20

EASY

APB System

Day 21

EASY

Day 21

Bonus Problem 1

EASY

Problem Designed by Nikolai Ternovoi