21 Days of RTL

Learn and practice design problems on QuickSilicon

Interested in joining the #100DaysofRTL trend but not sure where to begin? This free course offers the first 21 days, setting the groundwork for practical digital design skills covering both RTL and Testbench. The tailored series of questions covers various aspects of RTL design and verification, ranging from fundamental concepts such as a basic 2:1 multiplexer to more complex topics like round-robin arbiters.


Overview

Interested in joining the #100DaysofRTL trend but not sure where to begin? This free course offers the first 21 days, setting the groundwork for practical digital design skills covering both RTL and Testbench. The tailored series of questions covers various aspects of RTL design and verification, ranging from fundamental concepts such as a basic 2:1 multiplexer to more complex topics like round-robin arbiters.

What you'll learn

Various SystemVerilog language constructs useful for writing modern synthesisable RTL
Learn, develop and share RTL Design and Testbenches
Start from a basic mux to designing round-robin arbiters
Get working solutions in SystemVerilog

Skills you'll gain

RTL Design
Testbench Simulation
System Verilog
Fifos
Arbiters

Details to know

Course LanguageEnglish
Course PricingIt's free! Oh actually nothing is free, it's your valuable time!
Course ScheduleFlexible/Self Paced
Number of modules21
Name of the instructorRahul Behl

QuickSilicon

Registered Office
Shop No. 56 Block P NIT 5 Faridabad, Haryana - 121001
CIN: U72900HR2021PTC094537
Telephone No: +91-9923278283

21 Days of RTL

Learn and practice design problems on QuickSilicon

Interested in joining the #100DaysofRTL trend but not sure where to begin? This free course offers the first 21 days, setting the groundwork for practical digital design skills covering both RTL and Testbench. The tailored series of questions covers various aspects of RTL design and verification, ranging from fundamental concepts such as a basic 2:1 multiplexer to more complex topics like round-robin arbiters.


Overview

Interested in joining the #100DaysofRTL trend but not sure where to begin? This free course offers the first 21 days, setting the groundwork for practical digital design skills covering both RTL and Testbench. The tailored series of questions covers various aspects of RTL design and verification, ranging from fundamental concepts such as a basic 2:1 multiplexer to more complex topics like round-robin arbiters.

What you'll learn

Various SystemVerilog language constructs useful for writing modern synthesisable RTL
Learn, develop and share RTL Design and Testbenches
Start from a basic mux to designing round-robin arbiters
Get working solutions in SystemVerilog

Skills you'll gain

RTL Design
Testbench Simulation
System Verilog
Fifos
Arbiters

Details to know

Course LanguageEnglish
Course PricingIt's free! Oh actually nothing is free, it's your valuable time!
Course ScheduleFlexible/Self Paced
Number of modules21
Name of the instructorRahul Behl

QuickSilicon

Registered Office
Shop No. 56 Block P NIT 5 Faridabad, Haryana - 121001
CIN: U72900HR2021PTC094537
Telephone No: +91-9923278283