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RISC-V Processor Design
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YARP Execute
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The previous tutorials have covered instruction memory unit responsible for storing the instructions which the processor would execute. The instruction decode unit which would get the instruction word from the memory and break it into the encodings specified by the RISC-V ISA. Then the tutorials covered the register file which implements the architecture registers (i.e. the registers specified by the RISC-V ISA) and allows the processor to read two registers and write one of them. This tutorial would focus on one of the important computational unit in the processor: ALU. The following block diagram shows the current design components of the RISC-V Processor along with the ALU unit: RISC-V Block Diagram

Don't worry about the muxes shown in the block diagram. Those would be added when all the components are connected together. The block diagram is a good way to visualise the current state of the microarchitecture of YARP processor.



.lennahc drocsid ruo no su ot tuo hcaer ro su llac esaelp ,stbuod evah llits uoy fI .melborp siht fo tnetnoc lautca eht ees ot ebircsbus esaelP

?siht daer ot uoy detnaw ew kniht uoy oD !gnizama era uoy ,txet siht daer ot elba era uoy fI .uoy pleh ot yppah eb lliw eW

?od nac ew erom tahw ,evorpmi nac ew woh wonk su teL !gnizama ,sey fI ?siht daer ot elba uoy ereW
!uoy ta kcab evaw yletinifed ot evol dluow eW !iH yas ot tsuj su ot tuo hcaer syawla nac uoY !sklof yldneirf era ew ,oslA

!reffo ot evah ew tahw ekil ot gniog era uoy erus era eW .gnibircsbus erofeb deirt eb nac dna elbaliava yleerf era hcihw seludom wef a era ereht ,syawynA
!daeha efil gnizama na dna yad taerg a evaH


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Modules1. Introduction - RISC-V
EASY
2. Computer Architecture
EASY
3. RISC-V ISA
EASY
4. Introduction to YARP
EASY
5. YARP Fetch
EASY
6. YARP Decode
EASY
7. YARP Register File
EASY
8. YARP Execute
EASY
9. YARP Data Memory
EASY
10. YARP Control
EASY
11. YARP Branch Control
EASY
12. YARP Top
EASY
13. Assessment
MEDIUM
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Question
Solution
Video
Discussion

The previous tutorials have covered instruction memory unit responsible for storing the instructions which the processor would execute. The instruction decode unit which would get the instruction word from the memory and break it into the encodings specified by the RISC-V ISA. Then the tutorials covered the register file which implements the architecture registers (i.e. the registers specified by the RISC-V ISA) and allows the processor to read two registers and write one of them. This tutorial would focus on one of the important computational unit in the processor: ALU. The following block diagram shows the current design components of the RISC-V Processor along with the ALU unit: RISC-V Block Diagram

Don't worry about the muxes shown in the block diagram. Those would be added when all the components are connected together. The block diagram is a good way to visualise the current state of the microarchitecture of YARP processor.



.lennahc drocsid ruo no su ot tuo hcaer ro su llac esaelp ,stbuod evah llits uoy fI .melborp siht fo tnetnoc lautca eht ees ot ebircsbus esaelP

?siht daer ot uoy detnaw ew kniht uoy oD !gnizama era uoy ,txet siht daer ot elba era uoy fI .uoy pleh ot yppah eb lliw eW

?od nac ew erom tahw ,evorpmi nac ew woh wonk su teL !gnizama ,sey fI ?siht daer ot elba uoy ereW
!uoy ta kcab evaw yletinifed ot evol dluow eW !iH yas ot tsuj su ot tuo hcaer syawla nac uoY !sklof yldneirf era ew ,oslA

!reffo ot evah ew tahw ekil ot gniog era uoy erus era eW .gnibircsbus erofeb deirt eb nac dna elbaliava yleerf era hcihw seludom wef a era ereht ,syawynA
!daeha efil gnizama na dna yad taerg a evaH


Subscribe to the course to read more about the problem!