Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

The previous tutorials have covered instruction memory unit responsible for storing the instructions
which the processor would execute. The instruction decode unit which would get the instruction word
from the memory and break it into the encodings specified by the RISC-V ISA. Then the tutorials
covered the register file which implements the architecture registers (i.e. the registers specified
by the RISC-V ISA) and allows the processor to read two registers and write one of them.
This tutorial would focus on one of the important computational unit in the processor: ALU. The
following block diagram shows the current design components of the RISC-V Processor along with the
ALU unit:
![RISC-V Block Diagram](/riscvBlockDiagram.png)

Don't worry about the muxes shown in the block diagram. Those would be added when all the components
are connected together. The block diagram is a good way to visualise the current state of the
microarchitecture of YARP processor.
