Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

This flagship course on our website will help you learn RTL Design the right way. It is presented as a set of 26 engaging modules, each covering a different RTL and Microarchitecture Design technique to build your conceptual understanding. 

Hands-on RTL Design

SystemVerilog Testbench Introduction

SystemVerilog Testbench Architecture

APB Interface

APB Transaction

APB Generator

APB Driver

APB Driver Phase 2

APB Monitor

APB Scoreboard

APB Environment

APB Testbench Top

RISC-V Processor (YARP) Interface

YARP Transaction

YARP Generator

YARP Driver

YARP Data Memory Model

YARP Monitor

YARP Scoreboard

YARP Testbench Top

Hands-on course to learn SystemVerilog Testbenches. The course would teach you how to build fully functional and modern SystemVerilog based Testbenches. You would be building two fully functional testbenches starting right from Interface Specification all the way to building drivers, scoreboards, monitors and checkers and even integrating DPI calls to verify a RISC-V RV32I Processor!

Hands-on Testbench Design

Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

This comprehensive course offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA). Whether you're an aspiring computer architect or a seasoned developer looking to expand your knowledge, this course equips you with essential skills and hands-on experience to understand and design RISC-V based processors from scratch.

RISC-V Processor Design

Introduction

Running Simulations

Combinatorial Logic

Sequential Logic

D Flip-Flop

D Flip-Flop with Enable

Counter

Up-down Counter

Self Reloading Counter

Shift Register

A beginner-friendly course to master the widely accepted industry-standard language for RTL design

SystemVerilog for Design

Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

Interested in joining the #100DaysofRTL trend but not sure where to begin? This free course offers the first 21 days, setting the groundwork for practical digital design skills covering both RTL and Testbench. The tailored series of questions covers various aspects of RTL design and verification, ranging from fundamental concepts such as a basic 2:1 multiplexer to more complex topics like round-robin arbiters.

21 Days of RTL

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Hands-on RTL Design

Hands-on Testbench Design

RISC-V Processor Design

SystemVerilog for Design

21 Days of RTL

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Course Selection

Hands-on RTL Design

Hands-on RTL Design

Hands-on Testbench Design

Hands-on Testbench Design

RISC-V Processor Design

RISC-V Processor Design

SystemVerilog for Design

SystemVerilog for Design

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