This tutorial would cover the register file for the YARP core. The previous tutorials talked about the RISC-V ISA and the instruction memory from where our processor would fetch the instruction and use the decode block to decode the 32-bit fetched instruction as per the encodings given in the ISA. Out of those components, almost every instruction had an encoding for the registers specified by the ISA. Those were decoded as either the source registers (rs1, rs2) or the destination register (rd). Both the source registers and destination registers refer to one of 32 available architectural registers as specified by the RISC-V ISA. This tutorial would cover how the processor maintains each of these registers and how these can be read to obtain the value stored in the source registers or to written to store a value into the destination register.

Register File

As discussed above the register file is used to read the value stored into one of the architectural registers and even to write the value to one of the architecture register. Here is the quick recap of the six instruction types as defined by the RISC-V ISA and the way those encode the source or destination registers:

There are few instruction types which either don't read any source registers (U and J type) or don't write to the destination register (S and B type). The R-type instructions read the values from both the source register and write the result of the instruction to the destination register. The I-type instructions on the other hand just read the source register 1. The later tutorials would cover in-depth as to how these instruction compute their result. Other than the source and destination register it is also imperative to understand the length for each of the registers that would be implemented in the register file. The RISC-V ISA uses the term XLEN to denote the length of architectural registers present in the processor. For our processor the XLEN would be equal to 32, which means there are 32 registers, each of those would be 32-bit wide. Also, the RISC-V ISA mandates that the register 0 (X0) should be hardwired to 0 i.e. the register would always keep the value 0. Even if the instruction wants to write another value to X0, this value would be ignored and register X0 would continue to give the value 0. For more information, please refer to section "2.1 Programmers’ Model for Base Integer ISA" of the RISC-V ISA.

Design Requirements

The register file should allow reading the values of two register and writing to one register and as from the above encodings it is clear that the register needs to support ports to allow reading two source registers and writing to one of the register. The instruction encodings above would serve as the addresses from where the data would be read/written to. The register file should ensure that the register X0 is hardwired to 0.

Since the processor is single-cycle, it should be fine to allow write to take a cycle but the read data should be given on the same cycle which would be later used to during the execute phase.

Interface Definition

The register file would have the following interface definition:

• clk : Input clock signal (this is same as the processor clock)
• rs1_addr_i : 5-bit input address for the RS1 source register
• rs2_addr_i : 5-bit input address for the RS2 source register
• rd_addr_i : 5-bit input address for the RD destination register
• wr_en_i : 1-bit write enable signal input
• wr_data_i : 32-bit write data input
• rs1_data_o : 32-bit output data corresponding to RS1 register
• rs2_data_o : 32-bit output data corresponding to RS2 register