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You are leading a complex SoC which interacts with a lot of peripherals. As a result there is a need for an arbitration scheme to be used across the SoC. You decide to design a parameterized fixed priority arbitration scheme which grants a winner every cycle.

Design the parameterized single cycle arbiter module with fixed priority arbitration scheme. All the flops (if any) should be positive edge triggered with asynchronous resets.

Interface Definition

req_i : Input request vector to the arbiter
gnt_o : One-hot encoded signal for the winning request port

Interface Requirements

• Arbiter should grant a single winner (if any) every cycle
• The arbiter should use a fixed priority arbitration scheme
• Port[0] has the highest priority and priority decreases with incrementing port numbers

Sample Simulation

Explanation

• Cycle T1 : Reset is asserted

• Cycle T2 : Reset is de-asserted

• Cycle T3 : req_i is 0x0 - No incoming requests. gnt_o is also 0x0

• Cycle T4 : req_i is 0x3 - Requests at Port[0] and [1]. gnt_o is 0x1 as port[0] gets priority

• Cycle T5 : req_i is 0x6 - Requests at port[1] and [2]. gnt_o is 0x2 as port[1] gets priority

• Cycle T6 : req_i is 0xC - Requests at port[2] and [3]. gnt_o is 0x4 as port[2] wins

• Cycle T7 : req_i is 0x9 - Requests at port[0] and [3]. gnt_o is 0x1 as port[0] wins

• Cycle T8 : req_i is 0xE - Requests at port[1], [2] and [3]. gnt_o is 0x2 as port[1] wins

• Cycle T9 : req_i is 0xF - Requests at all the ports. gnt_o is 0x1 as port[0] wins