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RISCV Constraint

Polymorphism Example

## Constraint Randomization using Verilator
Verilator has been slowly adding support for constraint randomization and the recent 5.028
version adds the support for conditional constraints. I was excited to see this update and
right away jumped on using it to develop quick set of constraints to generate legal RV32I
instructions.

You can take a look at the code and play around with it to add more support.

### Would be happy to hear on how would you implement these set of constraints.


```verilog
// ----------------------------------------------------------------
// Constraint randomization to generate legal RV32I instructions
// ----------------------------------------------------------------

package riscv_pkg;

  typedef enum logic[6:0] {
    R_TYPE    = 7'h33,
    I_TYPE_0  = 7'h03,
    I_TYPE_1  = 7'h13,
    I_TYPE_2  = 7'h67,
    S_TYPE    = 7'h23,
    B_TYPE    = 7'h63,
    U_TYPE_0  = 7'h37,
    U_TYPE_1  = 7'h17,
    J_TYPE    = 7'h6F
  } riscv_op_t;

  // R Type funct3
  typedef enum logic[2:0] {
    ADD   = 3'h0,
    SLL   = 3'h1,
    SLT   = 3'h2,
    SLTU  = 3'h3,
    XOR   = 3'h4,
    SRX   = 3'h5,
    OR    = 3'h6,
    AND   = 3'h7
  } r_type_t;

  // I Type 0 funct3
  typedef enum logic[2:0] {
    LB    = 3'h0,
    LBU   = 3'h4,
    LH    = 3'h1,
    LHU   = 3'h5,
    LW    = 3'h2
  } i_type0_t;

  // I Type 1 funct3
  typedef enum logic[2:0] {
    ADDI  = 3'h0,
    SLLI  = 3'h1,
    SLTI  = 3'h2,
    SLTIU = 3'h3,
    XORI  = 3'h4,
    SRXI  = 3'h5,
    ORI   = 3'h6,
    ANDI  = 3'h7
  } i_type1_t;

  // I Type 2 funct3
  typedef enum logic[2:0] {
    JALR = 3'h0
  } i_type2_t;

  // S Type funct3
  typedef enum logic[2:0] {
    SB = 3'h0,
    SH = 3'h1,
    SW = 3'h2
  } s_type_t;

  // B Type funct3
  typedef enum logic[2:0] {
    BEQ  = 3'h0,
    BNE  = 3'h1,
    BLT  = 3'h4,
    BGE  = 3'h5,
    BLTU = 3'h6,
    BGEU = 3'h7
  } b_type_t;

  typedef enum logic[6:0] {
    LUI   = U_TYPE_0,
    AUIPC = U_TYPE_1
  } u_type_t;

endpackage

import riscv_pkg::*;
class rv32i_instr_gen;

  bit[31:0]         instruction;
  rand  riscv_op_t  opcode;
  rand  bit[4:0]    rd;
  rand  bit[2:0]    funct3;
  rand  bit[4:0]    rs1;
  rand  bit[4:0]    rs2;
  rand  bit[6:0]    funct7;
  rand  bit[11:0]   imm12;
  rand  bit[19:0]   imm20;

  function new ();
  endfunction

  // Ensure opcode is randomized to a legal value
  constraint legal_opcode {
    opcode inside {R_TYPE, I_TYPE_0, I_TYPE_1, I_TYPE_2,
                   S_TYPE, B_TYPE, U_TYPE_0, U_TYPE_1, J_TYPE};
  }

  // Randomize funct3 on the basis of the opcode field
  constraint legal_funct3 {
    if (opcode == R_TYPE) {
      funct3 inside {ADD, SLL, SLT, SLTU, XOR, SRX, OR, AND};
    } else if (opcode == I_TYPE_0) {
      funct3 inside {LB, LBU, LH, LHU, LW};
    } else if (opcode == I_TYPE_1) {
      funct3 inside {ADDI, SLLI, SLTI, SLTIU, XORI, SRXI, ORI, ANDI};
    } else if (opcode == I_TYPE_2) {
      funct3 == 0;
    } else if (opcode == S_TYPE) {
      funct3 inside {SB, SH, SW};
    } else if (opcode == B_TYPE) {
      funct3 inside {BEQ, BNE, BLT, BGE, BLTU, BGEU};
    }
  }

  // For R_TYPE, funct7 can take two separate values for ADD/SUB and SRL/SRA
  constraint legal_funct7 {
    if ((opcode == R_TYPE) && ((funct3 == ADD) || (funct3 == SRX))) {
      funct7 inside {7'h0, 7'h20};
    } else {
      funct7 == 7'h0;
    }
  }

  // Constraint the immediate field for SLLI, SRLI and SRAI
  constraint legal_imm12 {
    if (opcode == I_TYPE_1) {
      if (funct3 == SLLI) {
        imm12[11:5] == 7'h0;
      } else if (funct3 == SRXI) {
        imm12[11:5] inside {7'h0, 7'h20};
      }
    }
  }

  function void post_randomize ();
    string      gen_instr_msg;
    r_type_t    r_type_funct3;
    i_type0_t   i_type0_funct3;
    i_type1_t   i_type1_funct3;
    s_type_t    s_type_funct3;
    b_type_t    b_type_funct3;
    u_type_t    u_type_funct3;

    r_type_funct3 = r_type_t'(funct3);
    i_type0_funct3 = i_type0_t'(funct3);
    i_type1_funct3 = i_type1_t'(funct3);
    s_type_funct3 = s_type_t'(funct3);
    b_type_funct3 = b_type_t'(funct3);
    u_type_funct3 = u_type_t'(opcode);

    /* verilator lint_off CASEINCOMPLETE */
    // Construct the 32b instruction depending on the opcode field
    case (opcode)
      R_TYPE : begin
        instruction = {funct7, rs2, rs1, funct3, rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\tX%0d\n", opcode.name(), instruction, r_type_funct3.name(), rd, rs1, rs2);
        if ((funct3 == ADD) && (funct7 == 7'h20)) begin
          gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\tX%0d\n", opcode.name(), instruction, "SUB", rd, rs1, rs2);
        end else if ((funct3 == SRX) && (funct7 == 7'h20)) begin
          gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\tX%0d\n", opcode.name(), instruction, "SRA", rd, rs1, rs2);
        end else if (funct3 == SRX) begin
          gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\tX%0d\n", opcode.name(), instruction, "SRL", rd, rs1, rs2);
        end
      end
      I_TYPE_0 : begin
        instruction = {imm12, rs1, funct3, rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t%0d\n", opcode.name(), instruction, i_type0_funct3.name(), rd, rs1, imm12);
      end
      I_TYPE_1 : begin
        instruction = {imm12, rs1, funct3, rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t%0d\n", opcode.name(), instruction, i_type1_funct3.name(), rd, rs1, imm12);
        if ((funct3 == SRXI) && (imm12[11:5] == 7'h20)) begin
          gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t%0d\n", opcode.name(), instruction, "SRAI", rd, rs1, imm12);
        end else if (funct3 == SRXI) begin
          gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t%0d\n", opcode.name(), instruction, "SRLI", rd, rs1, imm12);
        end
      end
      I_TYPE_2 : begin
        instruction = {imm12, rs1, funct3, rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t%0d\n", opcode.name(), instruction, "JALR", rd, rs1, imm12);
      end
      S_TYPE : begin
        instruction = {imm12[11:5], rs2, rs1, funct3, imm12[4:0], opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t+%0d\n", opcode.name(), instruction, s_type_funct3.name(), rs1, rs2, imm12);
      end
      B_TYPE : begin
        instruction = {imm12[11], imm12[9:4], rs2, rs1, funct3, imm12[3:0], imm12[10], opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\tX%0d,\t+%0d\n", opcode.name(), instruction, b_type_funct3.name(), rs1, rs2, imm12);
      end
      U_TYPE_0,
      U_TYPE_1: begin
        instruction = {imm20, rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\t%0d\n", opcode.name(), instruction, u_type_funct3.name(), rd, imm20);
      end
      J_TYPE : begin
        instruction = {imm20[19], imm20[9:0], imm20[10], imm20[18:11], rd, opcode};
        gen_instr_msg = $sformatf ("*-* Generated\t%8s instruction:\t0x%8x: %5s X%0d,\t%0d\n", opcode.name(), instruction, "JAL", rd, imm20);
      end
    endcase
    /* verilator lint_on CASEINCOMPLETE */
    $write (gen_instr_msg);
  endfunction

endclass

module rv32i_instr ();

  rv32i_instr_gen gen;
  int rand_ok;

  initial begin
    gen = new();
    for (int i=0; i<25; i++) begin
      rand_ok = gen.randomize();
      if (rand_ok != 1) $stop;
    end
    $finish;
  end

endmodule
```
