VIPT Cache Introduction

Virtually Indexed Physically Tagged Cache

Welcome to the introductory lesson on the VIPT cache design RTL capstone project. Through this course we would design a virtually indexed and physically tagged 4-Way Set associative cache. This would be designed to be used as the Instruction Cache for a RISC-V Processor

The course would go deep into the Cache Architecture, Pipelining and even focus on designing the microarchitecture from scratch in SystemVerilog.

This video introduces you to the course and some of the key objectives. Through these set of lessons, you'd be exposed to various building blocks which make up the VIPT cache. You will be expected to design the various components, implement them in RTL and test the cache functionality through simulation testbenches and debug waveforms.

Without wasting any time, let's get on with it.

There is no coding exercise in this lesson, but make sure to watch the video and understand the various components of the VIPT cache and how they interact with each other. This would be crucial for the upcoming lessons where we would be designing these components in RTL.