VIPT Cache Introduction

VIPT Cache Parameters

SKY130 SRAM Macros

VIPT Cache Data Pipeline

VIPT Cache Replacement Policy

VIPT Cache Tag Pipeline

VIPT Cache Top

System Verilog for Design

This lesson would cover the microarchitecture and RTL design of the instruction data pipeline.
As a quick recap, the Virtually Indexed and Physically Tagged cache has the following parameters:

* Size: 4KB
* Number of ways: 4
* Cacheline size: 4B (32b)
* Number of sets: 256
* Page size granularity: 4KB

The data pipeline is responsible for storing the instruction data which would be utilised
by the processor for execution. In our case, this would simply mean the 32b instruction word
which are fetched from the memory and stored in the data RAMs. The data RAMs are also arranged
on per way basis to allow reading the data stored in each of the ways of the set. The data read
from the SRAMs is then flopped to the `T2` stage of the pipeline and then muxed out based on
the hit way information from the tag pipeline.

![VIPT Cache Top](/cache_top.webp)
