VIPT Cache Introduction

VIPT Cache Parameters

SKY130 SRAM Macros

VIPT Cache Data Pipeline

VIPT Cache Replacement Policy

VIPT Cache Tag Pipeline

VIPT Cache Top

System Verilog for Design

# Sky130 1KB SRAM Macro (1RW1R)

This lesson covers the Sky130 1KB SRAM macro which is a crucial building block for the VIPT cache design. The SRAM macro is an OpenRAM generated memory compiler instance designed for the Sky130 PDK. This SRAM will be used to store both the tag information and the instruction data for the cache.

## SRAM Specifications

The Sky130 1KB SRAM macro has the following specifications:

| Parameter | Value |
|-----------|-------|
| Memory Capacity | 1 KB (1024 bytes) |
| Word Count | 256 |
| Word Width | 32 bits |
| Address Width | 8 bits |
| Write Mask Bits | 4 (1 bit per byte) |
| Port 0 | 1 Read/Write (RW) Port |
| Port 1 | 1 Read-Only (R) Port |
| Technology | Sky130 PDK |
| Memory Type | Synchronous SRAM |

The SRAM provides two independent ports:
- **Port 0 (RW)**: Supports both read and write operations with byte-level write masking capability
- **Port 1 (R)**: Read-only port for simultaneous reads without blocking writes on Port 0

For the cache design, only Port 0 is utilized through the simplified top-level wrapper module.


Parameter	Value
Memory Capacity	1 KB (1024 bytes)
Word Count	256
Word Width	32 bits
Address Width	8 bits
Write Mask Bits	4 (1 bit per byte)
Port 0	1 Read/Write (RW) Port
Port 1	1 Read-Only (R) Port
Technology	Sky130 PDK
Memory Type	Synchronous SRAM