Day 17

Design and verify a valid/ready based memory interface slave. The interface should be able to generate the ready output after a random delay. Memory should be 16x32 bits wide.

Interface Definition

• Valid/ready protocol must be honoured
• The module should have the following interface:

module day17 (
  input       wire        clk,
  input       wire        reset,

  input       wire        req_i,        -> Valid request input remains asserted until ready is seen
  input       wire        req_rnw_i,    -> Read-not-write (1-read, 0-write)
  input       wire[3:0]   req_addr_i,   -> 4-bit Memory address
  input       wire[31:0]  req_wdata_i,  -> 32-bit write data
  output      wire        req_ready_o,  -> Ready output when request accepted
  output      wire[31:0]  req_rdata_o   -> Read data from memory
);

  // Memory array
  logic [15:0][31:0] mem;

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing the checks or the testbench code then I'd recommend the Hands-on RTL Design course. The course contains 25 RTL Design problems to help improve your design skills and comes with a 2-part video solution for every problem.