Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

# RISC-V Processor Design

Welcome to the introductory lesson on the RISC-V Processor Design course. Through this course
you would get to learn about Processor Design, Computer Architecture, RISC-V Instruction Set
Architecture and designing a RV32I Processor from scratch in SystemVerilog.

This video introduces you to the course and some of the key objectives. Through these set of
lessons, you'd be exposed to various building blocks which make up a single cycle processor.
You will be expected to design the various components, implement them in RTL and see the processor
come to life via waveforms and simulations.

Without wasting any time, let's get on with it.
