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Hands-on RTL Design

Learn and practice design problems on QuickSilicon

Handpicked questions which would improve your digital design skills! The curated list of questions cover different aspects of RTL design and verification. These questions span across multiple concepts varying from beginner to advance level.

Buy Now

Course modules

Atomic Counters
EASY
Learn why single-copy atomic operations are useful
Sneak Peek
Divide by 3
EASY
Will these serial inputs ever stop?
Sneak Peek
3-bit Palindrome
EASY
Discover when FSMs can be dangerous
Sneak Peek
Sequence Generator
EASY
Can do without any inputs
Start
Single Cycle Arbiters
EASY
Arbiters, every design needs one!
Sneak Peek
Events to APB
MEDIUM
Best way to learn about a protocol is to implement one
Start
Low Power Channel
HARD
Understand why some signals are asserted low
Sneak Peek
Two Pulses
MEDIUM
Serial inputs can be confusing
Sneak Peek
Clock Generator
EASY
A flop can do a lot more
Sneak Peek
Skid Buffer
HARD
Isn't as easy as it sounds
Sneak Peek
Least Recently Used
HARD
The cache ways are parameterizable!
Sneak Peek
Edge Capture
EASY
You gotta have one
Sneak Peek
One Shot
EASY
The easiest of the lot
Sneak Peek
Parallel to Serial
MEDIUM
An interesting take on parallel-to-serial converters
Sneak Peek
Running Average
MEDIUM
Gotta maintain that average
Sneak Peek
Big Endian Converter
EASY
Not every device reads the bytes in same order
Sneak Peek
Credits & Deadlock
HARD
A complex design can have complex scenarios
Sneak Peek
Ordering
HARD
You have to maintain the order while maximizing perf
Sneak Peek
Performance Counter
EASY
A counter which resets on read? Sounds cool.
Sneak Peek
Asynchronous Resets
MEDIUM
You thought synchronization was enough? Try this
Sneak Peek
Fifo Flush
HARD
How will flush complete if input data never stops?
Start
Buffering
HARD
Protocol conversions aren't that easy
Sneak Peek
Compression Engine
MEDIUM
Mantissa and exponent not always represent a floating point number
Sneak Peek
Perfect Squares
MEDIUM
Wait, what? We cant just multiply?
Sneak Peek
Cross correlation
EASY
A serial input stream can mean a lot of things?
Sneak Peek
System Verilog for Design
EASY
A guide to using System Verilog for Design!
Start

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QuickSilicon

Registered Office
Shop No. 56 Block P NIT 5 Faridabad, Haryana - 121001
CIN: U72900HR2021PTC094537
Telephone No: +91-8700725274
QuickSilicon
Course Modules
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Sign Up
Log InSign Up

Hands-on RTL Design

Learn and practice design problems on QuickSilicon

Handpicked questions which would improve your digital design skills! The curated list of questions cover different aspects of RTL design and verification. These questions span across multiple concepts varying from beginner to advance level.

Buy Now

Course modules

Atomic Counters
EASY
Learn why single-copy atomic operations are useful
Sneak Peek
Divide by 3
EASY
Will these serial inputs ever stop?
Sneak Peek
3-bit Palindrome
EASY
Discover when FSMs can be dangerous
Sneak Peek
Sequence Generator
EASY
Can do without any inputs
Start
Single Cycle Arbiters
EASY
Arbiters, every design needs one!
Sneak Peek
Events to APB
MEDIUM
Best way to learn about a protocol is to implement one
Start
Low Power Channel
HARD
Understand why some signals are asserted low
Sneak Peek
Two Pulses
MEDIUM
Serial inputs can be confusing
Sneak Peek
Clock Generator
EASY
A flop can do a lot more
Sneak Peek
Skid Buffer
HARD
Isn't as easy as it sounds
Sneak Peek
Least Recently Used
HARD
The cache ways are parameterizable!
Sneak Peek
Edge Capture
EASY
You gotta have one
Sneak Peek
One Shot
EASY
The easiest of the lot
Sneak Peek
Parallel to Serial
MEDIUM
An interesting take on parallel-to-serial converters
Sneak Peek
Running Average
MEDIUM
Gotta maintain that average
Sneak Peek
Big Endian Converter
EASY
Not every device reads the bytes in same order
Sneak Peek
Credits & Deadlock
HARD
A complex design can have complex scenarios
Sneak Peek
Ordering
HARD
You have to maintain the order while maximizing perf
Sneak Peek
Performance Counter
EASY
A counter which resets on read? Sounds cool.
Sneak Peek
Asynchronous Resets
MEDIUM
You thought synchronization was enough? Try this
Sneak Peek
Fifo Flush
HARD
How will flush complete if input data never stops?
Start
Buffering
HARD
Protocol conversions aren't that easy
Sneak Peek
Compression Engine
MEDIUM
Mantissa and exponent not always represent a floating point number
Sneak Peek
Perfect Squares
MEDIUM
Wait, what? We cant just multiply?
Sneak Peek
Cross correlation
EASY
A serial input stream can mean a lot of things?
Sneak Peek
System Verilog for Design
EASY
A guide to using System Verilog for Design!
Start

About

Legal
Privacy
Contact Us

Reach us at

LinkedIn
Instagram
Twitter
Facebook
Gmail

QuickSilicon

Registered Office
Shop No. 56 Block P NIT 5 Faridabad, Haryana - 121001
CIN: U72900HR2021PTC094537
Telephone No: +91-8700725274