This flagship course on our website will help you learn RTL Design the right way. It is presented as a set of 31 engaging modules, each covering a different RTL and Microarchitecture Design technique to build your conceptual understanding.
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$65 · 1 year access
Build the practical skills described in this course
34 handpicked questions to up your interview game
Learn about skid buffers, fifos, valid-ready protocol and a lot more
Designing complex microarchitectures with focus on PPA
Converting microarchitecture details into real-world synthesizble RTL
Various industry standard timing optimisation challenges
Explore the course content, track your progress, and get answers to your questions
Everything you need to know about this course
This flagship course on our website will help you learn RTL Design the right way. It is presented as a set of 31 engaging modules, each covering a different RTL and Microarchitecture Design technique to build your conceptual understanding.
Learn from an industry expert with 10+ years of experience
What you'll be able to do after completing this course
The curriculum
34 modules across 3 sections. Explore in order, or find the problem you want to solve.
5 modules
Discover when FSMs can be dangerous
Counters
You gotta have one
The easiest of the lot
Not every device reads the bytes in same order
A guide to using System Verilog for Design!
20 modules · 3 free
Learn why single-copy atomic operations are useful
Counters · Area
Will these serial inputs ever stop?
Can do without any inputs
Counters
Arbiters, every design needs one!
Best way to learn about a protocol is to implement one
FSMs · AMBA
Understand why some signals are asserted low
FSMs · FIFOs · AMBA · Power
Serial inputs can be confusing
Counters
A flop can do a lot more
The cache ways are parameterizable!
An interesting take on parallel-to-serial converters
FSMs
Gotta maintain that average
FIFOs · Power
A complex design can have complex scenarios
FIFOs · Skid Buffer
You have to maintain the order while maximizing perf
FIFOs · Timing
A counter which resets on read? Sounds cool.
Counters
You thought synchronization was enough? Try this
Timing
How will flush complete if input data never stops?
FIFOs · Power · Area
Protocol conversions aren't that easy
FSMs
Mantissa and exponent not always represent a floating point number
Wait, what? We cant just multiply?
Counters
A serial input stream can mean a lot of things?
Counters
9 modules · 4 free
Isn't as easy as it sounds
Skid Buffer · Timing
Implement a fast data muxing logic
Timing
Read from fifo is timing critical
Timing
Implement the fastest find first set
Timing
How hard can it be?
Timing
Building packet decoders isn’t fun
Timing
Pop is a multi-bit thermometer encoded
FIFO · Timing
Merge the data in fifo order
FIFO · Timing
Track IDs inside the fifo
FIFO · Timing