Hands-On RTL design for Networking Systems
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$49 · 1 year access
Build the practical skills described in this course
Problemset specialized in design patterns from the world of networking chips
Directly inspired by real world silicon and big tech interview questions
Covers various sub-topics ranging from simple gearboxes to complex packet parsers,arbiters and timing logic.
Power, performance and area tradeoffs to be handled in each problem
Course is available only in System Verilog (Get video explanations and working solutions in Only SystemVerilog)
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Everything you need to know about this course
Hands-On RTL design for Networking Systems
Learn from an industry expert with 6+ years of experience
What you'll be able to do after completing this course
The curriculum
22 modules. Explore in order, or find the problem you want to solve.
Change lanes with ease: Build a gearbox for seamless data width conversion!
gearboxes
Time to gear down
gearboxes
Shift gears with confidence: Design a robust gearbox for seamless data flow!
gearboxes · flow control
No byte left behind: Pack your data for a perfect output stream!
wide datapaths · non-uniform datapaths
Enqueue more, dequeue smart: Build a flexible FIFO for bursty data!
custom FIFO design
Switch from space to time: Multiplex your data with context clarity!
wide datapaths · context switching
Keep every thread in sync: Track and update counters with memory efficiency!
context switching
Keep your datapath clean: Drop the garbage, pass only the good packets!
packet processing
Keep the data flowing: Build a fair and efficient arbiter for high-speed traffic!
arbiters
Upgrade your arbitration: Smarter, fairer, and more flexible bandwidth sharing!
arbiters
Know your numbers: Track and report average command latency with precision!
performance measurement
Parse with precision: Extract fields from packets like a protocol pro!
packet parsing
Decode the details: Extract key fields from real TCP packets with smart parsing!
packet parsing
Delay with efficiency: Save power while keeping your data on time!
power analysis
Master memory fragmentation: Build a smart FIFO for many queues, one memory!
shared buffers
Find the frame: Mark, extract, and validate packets in a high-speed data stream!
wide datapaths · protocol parsing
Stream smarter: Build a pipeline that accumulates results with black-box magic!
black-box integration
Stay within bounds: Enforce smooth and penalty-free data transmission!
timing and measurement · bandwidth management
Track the extremes: Monitor min and max with smart threshold handling!
statistics measurement · signed arithmetic
Master timing: Build a UART baud rate generator in hardware!
timing and measurement
Precision timing: Build a timer that beats rounding errors!
timing and measurement
Crack the code: Build a hardware CRC checksum engine!
finite field arithmetic · error detection