Counting Time 1

DESCRIPTION:
One of the most unique aspects of working on designs in the networking or communication domain is the concept of time and rate. These concepts cannot be explained as simple mathematical operations. They are also not limited to a sequence of steps or transactions following an algorithm. Timers are unique in the sense that they are perpetually running as long as the device is powered on. A good timer is differentiated from a bad one based on how closely it achieves the required data rate or frequency. At a system level, even more emergent phenomena like Jitter and Wander are visible. They are not easy to visualize and can wreak havoc in large scale communication systems.

Understanding the most complex timing systems is way beyond this avenue, however we shall try to model some of the intricacies and challenges of working with timers in this problem and the next.

Most students of digital design, while preparing for an interview might have come across fancy clock divider circuits that perform tricky and clever manipulations to clocks and achieve non standard divider ratios.

In practical systems, many of those circuits don’t make much sense because routing a clock through flops and gates to generate another clock is criminally inefficient and the STA engineer’s biggest nightmare.

What is a lot more common though, is to have one fast clock, and use some logic to generate a clock_enable signal at the exact rate required for our design’s operation. This way, any number of ‘rates’ of operation can be achieved within the design using the same clock without requiring any clock domain crossing logic.

How to accurately generate this clock_enable at the exact rate required is what we will be investigating in this problem and the next.

PROBLEM STATEMENT:
Let’s start with a simple baud rate generator for a UART.