Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

You are tasked to design a circuit which would detect a 3-bit palindrome sequence from incoming
stream of bits.

Palindrome code is a sequence of characters which reads the same backward as forward. For example,
the following are palindromes: 101, 010, 111, 000, etc.

All the flops should be positive edge triggered with asynchronous resets (if any).

## Interface Definition

```
x_i : Input stream of bits to the circuit

palindrome_o : Output to signal that the current bit and the last two bits together form a
               palindrome
```



Palindrome 3b