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Async Resets
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You are asked to design a circuit which would avoid boot-up issues in silicon during asynchronous
reset deassertion. The circuit takes an asynchronous reset as input which is synchronised to the
clk domain. The circuit is responsible for driving two signals:
release_reset_o: This signal should be asserted when it is safe to deassert the reset to the rest of the circuitgate_clk_o: This circuit would gate the clock to the rest of the circuit
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System Verilog
Verilog
VHDL
Sublime
Emacs
Sublime
Vim
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY