Asynchronous Resets

You are asked to design a circuit which would avoid boot-up issues in silicon during asynchronous reset deassertion. The circuit takes an asynchronous reset as input which is synchronised to the clk domain. The circuit is responsible for driving two signals:

• release_reset_o: This signal should be asserted when it is safe to deassert the reset to the rest of the circuit
• gate_clk_o: This circuit would gate the clock to the rest of the circuit