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Atomic Counters
NOT SUBMITTED
While working on the next generation SoC you were asked to design a 64-bit event counter which would be interfaced with a 32-bit bus controlled via a microcontroller. The 64-bit counter is incremented whenever a trigger input is seen. Given that the counter is read by a 32-bit bus, a full 64-bit read of the counter needs two 32-bit accesses. It is important that these two accesses should be single-copy atomic.
Design the 64-bit counter module and the appropriate interfacing mechanism to ensure single-copy atomic counter read operations.
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System Verilog
Verilog
VHDL
Sublime
Emacs
Sublime
Vim
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY