Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Breaking a large vector into a combination of mantissa and exponent is a frequently used technique
to compress data. Using mantissa and exponent reduces the number of bits needed to represent the
vector with some impact on the accuracy. 

Rohan wants to deploy a similar scheme where he wants a 24-bit vector to be compressed into a
12-bit mantissa and a 4-bit exponent. The resultant vector can be obtained using the combination
of mantissa and exponent in the following manner:

```c
if (exponent == 0) then
  vector = mantissa
else
  vector = {1'b1, mantissa, {exponent-1{0}}}
end
```

