Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Sam is a fan of the AMBA APB protocol and has taken up the challenge to design
a block which converts certain input events to APB transactions. The design takes
three different inputs and generates an APB transaction to a single slave. Whenever
any input is asserted, Sam wants to send out an APB transaction to an address
reserved for the particular event. Sam needs your help to design the events to
APB converter.

All the flops (if any) should be positive edge triggered with asynchronous resets.

## Interface Definition
- The block takes three single bit inputs:
  ```
  event_a_i
  event_b_i
  event_c_i
  ```
- The output APB transaction uses the following signals:
  ```
  apb_psel_o
  apb_penable_o
  apb_paddr_o[31:0]
  apb_pwrite_o
  apb_pwdata_o[31:0]
  apb_pready_i
  ```
  The APB transaction should be generated whenever any of the input event is asserted.
  The generated APB transactions should always be an APB write transaction. Hence the
  interface doesn't contain the `apb_prdata_i` input.

![eventsToAPB_block_diagram](/events_to_apb_bd.webp)

## Interface Requirements
- The APB transaction must comply with the [AMBA APB protocol specifications](https://developer.arm.com/documentation/ihi0024/c)
- The three event inputs are mutually exclusive i.e. there can be atmost one event
  asserted on a cycle
- The APB transaction generated due to Event A should be sent to address 0xABBA0000
- The APB transaction generated due to Event B should be sent to address 0xBAFF0000
- The APB transaction generated due to Event C should be sent to address 0xCAFE0000
- The write data should give the count of the number of events seen since the last write for that
  particular event
- The APB interface guarantees that the `pready` signal would be asserted within 10 cycles for a
  particular transaction without any `pslverr`. Hence the interface doesn't contain the `pslverr`
  input
- Back to back APB transactions aren't supported by interface hence there should a cycle
  gap before the next APB transaction is generated
- The event input interface guarantees fairness amongst the three events such that there
  cannot be more than 10 pending events for any input event

Note: The above fairness scheme allows you to implement the address selection logic for the APB
      request in any given order of priority for the inputs.

## Sample Simulation
![events_To_APB](/events_to_apb.webp)


Sam is a fan of the AMBA APB protocol and has taken up the challenge to design
a block which converts certain input events to APB transactions. The design takes
three different inputs and generates an APB transaction to a single slave. Whenever
any input is asserted, Sam wants to send out an APB transaction to an address
reserved for the particular event. Sam needs your help to design the events to
APB converter.

All the flops (if any) should be positive edge triggered with asynchronous resets.



## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Events to APB - RTL
// --------------------------------------------------------

module events_to_apb (
  input   logic         clk,
  input   logic         reset,

  input   logic         event_a_i,
  input   logic         event_b_i,
  input   logic         event_c_i,

  output  logic         apb_psel_o,
  output  logic         apb_penable_o,
  output  logic [31:0]  apb_paddr_o,
  output  logic         apb_pwrite_o,
  output  logic [31:0]  apb_pwdata_o,
  input   logic         apb_pready_i

);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  typedef enum logic[1:0] {ST_IDLE, ST_SETUP, ST_ACCESS} apb_state_t;
  typedef enum logic[31:0] {
    EVENT_A_ADDR = 32'hABBA_0000,
    EVENT_B_ADDR = 32'hBAFF_0000,
    EVENT_C_ADDR = 32'hCAFE_0000} apb_addr_t;

  logic       apb_psel;
  logic       apb_penable;
  logic[31:0] apb_paddr;
  logic       apb_pwrite;
  logic       apb_pwdata_en;
  logic[31:0] apb_pwdata;

  logic[31:0] apb_pwdata_q;

  logic[31:0] paddr_q;
  logic[31:0] nxt_paddr;

  apb_state_t state_q;
  apb_state_t nxt_state;
  logic       apb_state_idle;
  logic       apb_state_setup;
  logic       apb_state_access;

  logic       event_seen;

  logic [3:0] event_a_count_q;
  logic [3:0] nxt_event_a_count;

  logic [3:0] event_b_count_q;
  logic [3:0] nxt_event_b_count;

  logic [3:0] event_c_count_q;
  logic [3:0] nxt_event_c_count;

  logic       event_a_sel;
  logic       event_b_sel;
  logic       event_c_sel;

  assign event_seen = |{event_a_i, event_b_i, event_c_i,
                        event_a_count_q, event_b_count_q, event_c_count_q};

  always_ff @(posedge clk or posedge reset)
    if (reset)
      state_q <= ST_IDLE;
    else
      state_q <= nxt_state;

  // --------------------------------------------------------
  // APB state machine
  // --------------------------------------------------------
  always_comb begin
    nxt_paddr = paddr_q;
    case (state_q)
      ST_IDLE: begin
        if (event_seen) begin
          nxt_state = ST_SETUP;
          nxt_paddr = (event_a_i | (|event_a_count_q)) ? EVENT_A_ADDR :
                      (event_b_i | (|event_b_count_q)) ? EVENT_B_ADDR :
                                                         EVENT_C_ADDR;
        end else begin
          nxt_state = ST_IDLE;
        end
      end
      ST_SETUP: begin
        nxt_state = ST_ACCESS;
      end
      ST_ACCESS: begin
        if (apb_pready_i)
          nxt_state = ST_IDLE;
        else
          nxt_state = ST_ACCESS;
      end
      default: nxt_state = ST_IDLE;
    endcase
  end

  assign apb_state_idle   = (state_q == ST_IDLE);
  assign apb_state_setup  = (state_q == ST_SETUP);
  assign apb_state_access = (state_q == ST_ACCESS);

  assign apb_psel    = apb_state_setup | apb_state_access;
  assign apb_penable = apb_state_access;
  assign apb_pwrite  = 1'b1;

  // --------------------------------------------------------
  // APB Address
  // --------------------------------------------------------
  always_ff @(posedge clk or posedge reset)
    if (reset)
      paddr_q <= EVENT_A_ADDR;
    else
      paddr_q <= nxt_paddr;

  assign apb_paddr = paddr_q;

  assign event_a_sel = (nxt_paddr == EVENT_A_ADDR);
  assign event_b_sel = (nxt_paddr == EVENT_B_ADDR);
  assign event_c_sel = (nxt_paddr == EVENT_C_ADDR);

  // --------------------------------------------------------
  // APB Write Data
  // --------------------------------------------------------
  always_ff @(posedge clk or posedge reset)
    if (reset) begin
      event_a_count_q <= 4'h0;
      event_b_count_q <= 4'h0;
      event_c_count_q <= 4'h0;
    end else begin
      event_a_count_q <= nxt_event_a_count;
      event_b_count_q <= nxt_event_b_count;
      event_c_count_q <= nxt_event_c_count;
    end

  assign nxt_event_a_count = event_a_sel & apb_state_setup ? {3'h0, event_a_i} : event_a_count_q + {3'h0, event_a_i};
  assign nxt_event_b_count = event_b_sel & apb_state_setup ? {3'h0, event_b_i} : event_b_count_q + {3'h0, event_b_i};
  assign nxt_event_c_count = event_c_sel & apb_state_setup ? {3'h0, event_c_i} : event_c_count_q + {3'h0, event_c_i};

  assign apb_pwdata = (event_a_sel) ? 32'(nxt_event_a_count) :
                      (event_b_sel) ? 32'(nxt_event_b_count) :
                      (event_c_sel) ? 32'(nxt_event_c_count) :
                                      32'h0;

  assign apb_pwdata_en = apb_state_idle & event_seen;
  always_ff @(posedge clk or posedge reset)
    if (reset)
      apb_pwdata_q <= 32'h0;
    else if (apb_pwdata_en)
      apb_pwdata_q <= apb_pwdata;

  // --------------------------------------------------------
  // Output Assignments
  // --------------------------------------------------------
  assign apb_psel_o     = apb_psel;
  assign apb_penable_o  = apb_penable;
  assign apb_paddr_o    = apb_paddr;
  assign apb_pwrite_o   = apb_pwrite;
  assign apb_pwdata_o   = apb_pwdata_q;


endmodule
```

-----------
## Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Events to APB - RTL
// --------------------------------------------------------

module events_to_apb (
  input   wire         clk,
  input   wire         reset,

  input   wire         event_a_i,
  input   wire         event_b_i,
  input   wire         event_c_i,

  output  wire         apb_psel_o,
  output  wire         apb_penable_o,
  output  wire [31:0]  apb_paddr_o,
  output  wire         apb_pwrite_o,
  output  wire [31:0]  apb_pwdata_o,
  input   wire         apb_pready_i

);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  localparam ST_IDLE   = 2'b00;
  localparam ST_SETUP  = 2'b01;
  localparam ST_ACCESS = 2'b10;

  localparam EVENT_A_ADDR = 32'hABBA_0000;
  localparam EVENT_B_ADDR = 32'hBAFF_0000;
  localparam EVENT_C_ADDR = 32'hCAFE_0000;

  wire       apb_psel;
  wire       apb_penable;
  wire[31:0] apb_paddr;
  wire       apb_pwrite;
  wire       apb_pwdata_en;
  wire[31:0] apb_pwdata;

  reg [31:0] apb_pwdata_q;

  reg [31:0] paddr_q;
  reg [31:0] nxt_paddr;

  reg [1:0]  state_q;
  reg [1:0]  nxt_state;
  wire       apb_state_idle;
  wire       apb_state_setup;
  wire       apb_state_access;

  wire       event_seen;

  reg  [3:0] event_a_count_q;
  wire [3:0] nxt_event_a_count;

  reg  [3:0] event_b_count_q;
  wire [3:0] nxt_event_b_count;

  reg  [3:0] event_c_count_q;
  wire [3:0] nxt_event_c_count;

  wire       event_a_sel;
  wire       event_b_sel;
  wire       event_c_sel;

  assign event_seen = |{event_a_i, event_b_i, event_c_i,
                        event_a_count_q, event_b_count_q, event_c_count_q};

  always @(posedge clk or posedge reset)
    if (reset)
      state_q <= ST_IDLE;
    else
      state_q <= nxt_state;

  // --------------------------------------------------------
  // APB state machine
  // --------------------------------------------------------
  always @(*) begin
    nxt_paddr = paddr_q;
    case (state_q)
      ST_IDLE: begin
        if (event_seen) begin
          nxt_state = ST_SETUP;
          nxt_paddr = (event_a_i | (|event_a_count_q)) ? EVENT_A_ADDR :
                      (event_b_i | (|event_b_count_q)) ? EVENT_B_ADDR :
                                                         EVENT_C_ADDR;
        end else begin
          nxt_state = ST_IDLE;
        end
      end
      ST_SETUP: begin
        nxt_state = ST_ACCESS;
      end
      ST_ACCESS: begin
        if (apb_pready_i)
          nxt_state = ST_IDLE;
        else
          nxt_state = ST_ACCESS;
      end
      default: nxt_state = ST_IDLE;
    endcase
  end

  assign apb_state_idle   = (state_q == ST_IDLE);
  assign apb_state_setup  = (state_q == ST_SETUP);
  assign apb_state_access = (state_q == ST_ACCESS);

  assign apb_psel    = apb_state_setup | apb_state_access;
  assign apb_penable = apb_state_access;
  assign apb_pwrite  = 1'b1;

  // --------------------------------------------------------
  // APB Address
  // --------------------------------------------------------
  always @(posedge clk or posedge reset)
    if (reset)
      paddr_q <= EVENT_A_ADDR;
    else
      paddr_q <= nxt_paddr;

  assign apb_paddr = paddr_q;

  assign event_a_sel = (nxt_paddr == EVENT_A_ADDR);
  assign event_b_sel = (nxt_paddr == EVENT_B_ADDR);
  assign event_c_sel = (nxt_paddr == EVENT_C_ADDR);

  // --------------------------------------------------------
  // APB Write Data
  // --------------------------------------------------------
  always @(posedge clk or posedge reset)
    if (reset) begin
      event_a_count_q <= 4'h0;
      event_b_count_q <= 4'h0;
      event_c_count_q <= 4'h0;
    end else begin
      event_a_count_q <= nxt_event_a_count;
      event_b_count_q <= nxt_event_b_count;
      event_c_count_q <= nxt_event_c_count;
    end

  assign nxt_event_a_count = event_a_sel & apb_state_setup ? {3'h0, event_a_i} : event_a_count_q + {3'h0, event_a_i};

  assign nxt_event_b_count = event_b_sel & apb_state_setup ? {3'h0, event_b_i} : event_b_count_q + {3'h0, event_b_i};

  assign nxt_event_c_count = event_c_sel & apb_state_setup ? {3'h0, event_c_i} : event_c_count_q + {3'h0, event_c_i};

  assign apb_pwdata = (event_a_sel) ? 32'(nxt_event_a_count) :
                      (event_b_sel) ? 32'(nxt_event_b_count) :
                      (event_c_sel) ? 32'(nxt_event_c_count) :
                                                    32'h0;

  assign apb_pwdata_en = apb_state_idle & event_seen;
  always @(posedge clk or posedge reset)
    if (reset)
      apb_pwdata_q <= 32'h0;
    else if (apb_pwdata_en)
      apb_pwdata_q <= apb_pwdata;

  // --------------------------------------------------------
  // Output Assignments
  // --------------------------------------------------------
  assign apb_psel_o     = apb_psel;
  assign apb_penable_o  = apb_penable;
  assign apb_paddr_o    = apb_paddr;
  assign apb_pwrite_o   = apb_pwrite;
  assign apb_pwdata_o   = apb_pwdata_q;


endmodule
```

-----------
## VHDL

```vhdl
-- --------------------------------------------------------
-- Copyright (C) quicksilicon.io - All Rights Reserved
--
-- Unauthorized copying of this file, via any medium is
-- strictly prohibited
-- Proprietary and confidential
-- --------------------------------------------------------
--
-- --------------------------------------------------------
-- Events to APB - RTL
-- --------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity events_to_apb is
  port (
    clk           : in  std_logic;
    reset         : in  std_logic;

    event_a_i     : in  std_logic;
    event_b_i     : in  std_logic;
    event_c_i     : in std_logic;

    apb_psel_o    : out std_logic;
    apb_penable_o : out std_logic;
    apb_paddr_o   : out std_logic_vector(31 downto 0);
    apb_pwrite_o  : out std_logic;
    apb_pwdata_o  : out std_logic_vector(31 downto 0);
    apb_pready_i  : in  std_logic
  );
end events_to_apb;

  -- --------------------------------------------------------
  -- Internal wire and regs
  -- --------------------------------------------------------
  architecture logic of events_to_apb is
  type state_t is (ST_IDLE, ST_SETUP, ST_ACCESS);

  signal state_q           : state_t;
  signal nxt_state         : state_t;



  constant EVENT_A_ADDR    : std_logic_vector(31 downto 0) := X"ABBA_0000";
  constant EVENT_B_ADDR    : std_logic_vector(31 downto 0) := X"BAFF_0000";
  constant EVENT_C_ADDR    : std_logic_vector(31 downto 0) := X"CAFE_0000";

  signal apb_psel          : std_logic;
  signal apb_penable       : std_logic;
  signal apb_paddr         : std_logic_vector(31 downto 0);
  signal apb_pwrite        : std_logic;

  signal apb_pwdata        : std_logic_vector(31 downto 0);
  signal apb_pwdata_q      : std_logic_vector(31 downto 0);

  signal paddr_q           : std_logic_vector(31 downto 0);
  signal nxt_paddr         : std_logic_vector(31 downto 0);

  signal apb_state_setup   : std_logic;
  signal apb_state_access  : std_logic;

  signal event_seen        : std_logic;
  signal event_a_count_q   : unsigned(3 downto 0);
  signal nxt_event_a_count : unsigned(3 downto 0);

  signal event_b_count_q   : unsigned(3 downto 0);
  signal nxt_event_b_count : unsigned(3 downto 0);

  signal event_c_count_q   : unsigned(3 downto 0);
  signal nxt_event_c_count : unsigned(3 downto 0);

  signal event_a_sel       : std_logic;
  signal event_b_sel       : std_logic;
  signal event_c_sel       : std_logic;

  begin


    event_seen <= '0' when (((event_a_i or event_b_i or event_c_i) = '0') and
                            ((event_a_count_q or event_b_count_q or
                            event_c_count_q) = "000"))  else '1';

    process (clk, reset) is
    begin
      if reset = '1' then
        state_q     <= ST_IDLE;
      elsif rising_edge(clk) then
        state_q     <= nxt_state;
      end if;
    end process;

    -- --------------------------------------------------------
    --  APB state machine
    -- --------------------------------------------------------
    process (state_q, event_seen, apb_pready_i) is
    begin
      nxt_paddr <= paddr_q;
      case state_q is
        when ST_IDLE =>
          if (event_seen='1') then
            if ((event_c_i /= '0') or (event_c_count_q /= "0000")) then
              nxt_paddr <= EVENT_C_ADDR;
            elsif ((event_b_i /= '0') or (event_b_count_q /= "0000")) then
              nxt_paddr <= EVENT_B_ADDR;
            else
              nxt_paddr <= EVENT_A_ADDR;
            end if;
            nxt_state <= ST_SETUP;
          else
            nxt_state <= ST_IDLE;
          end if;
        when ST_SETUP =>
          nxt_state <= ST_ACCESS;
        when ST_ACCESS =>
          if(apb_pready_i = '1') then
            nxt_state <= ST_IDLE;
          else
            nxt_state <=  ST_ACCESS;
          end if;
        when others =>
          nxt_state <= ST_IDLE;
      end case;
    end process;

    apb_state_setup  <= '1' when state_q = ST_SETUP else '0';
    apb_state_access <= '1' when state_q = ST_ACCESS else '0';

    apb_psel    <= '1' when (apb_state_setup or apb_state_access) = '1' else '0';
    apb_penable <= apb_state_access;
    apb_pwrite  <= apb_state_access;

  -- --------------------------------------------------------
  -- APB Address
  -- --------------------------------------------------------
    process (clk, reset) is
      begin
        if reset = '1' then
          paddr_q     <= EVENT_A_ADDR;
        elsif rising_edge(clk) then
          paddr_q     <= nxt_paddr;
        end if;
      end process;

      apb_paddr <= (paddr_q) when (apb_state_access = '1') else (X"0000_0000");

      event_a_sel <= '1' when (apb_state_setup = '1') and (paddr_q = EVENT_A_ADDR) else '0';
      event_b_sel <= '1' when (apb_state_setup = '1') and (paddr_q = EVENT_B_ADDR) else '0';
      event_c_sel <= '1' when (apb_state_setup = '1') and (paddr_q = EVENT_C_ADDR) else '0';

  -- --------------------------------------------------------
  -- APB Write Data
  -- --------------------------------------------------------
    process (clk, reset) is
      begin
        if reset = '1' then
          event_a_count_q <= "0000";
          event_b_count_q <= "0000";
          event_c_count_q <= "0000";
        elsif rising_edge(clk) then
          event_a_count_q <= nxt_event_a_count;
          event_b_count_q <= nxt_event_b_count;
          event_c_count_q <= nxt_event_c_count;
        end if;
      end process;

      nxt_event_a_count <= ("000" & event_a_i) when event_a_sel = '1'      else
                             event_a_count_q + "0001" when event_a_i = '1' else
                             event_a_count_q;

      nxt_event_b_count <= ("000" & event_b_i) when event_b_sel = '1'      else
                             event_b_count_q + "0001" when event_b_i = '1' else
                             event_b_count_q;

      nxt_event_c_count <= ("000" & event_c_i) when event_c_sel = '1'      else
                             event_c_count_q + "0001" when event_c_i = '1' else
                             event_c_count_q;

      apb_pwdata <= (X"0000_000" & std_logic_vector(event_a_count_q)) when (event_a_sel = '1') else
                    (X"0000_000" & std_logic_vector(event_b_count_q)) when (event_b_sel = '1') else
                    (X"0000_000" & std_logic_vector(event_c_count_q)) when (event_c_sel = '1') else
                    (others => '0');

    process (clk, reset) is
      begin
        if reset = '1' then
          apb_pwdata_q     <= (others => '0');
        elsif rising_edge(clk) and (apb_state_setup = '1') then
          apb_pwdata_q     <= apb_pwdata;
        end if;
      end process;
    -- -------------------------------------------------------
    -- Output assignments
    -- --------------------------------------------------------
      apb_psel_o     <= apb_psel;
      apb_penable_o  <= apb_penable;
      apb_paddr_o    <= apb_paddr;
      apb_pwrite_o   <= apb_pwrite;
      apb_pwdata_o   <= apb_pwdata_q;

  end architecture;
```



I spent some time solving the Events to APB problem on QuickSilicon.in

This was an interesting RTL Design problem which involved designing an APB protocol to service certain incoming events. Here are a few more details from synthesizing my design:

- Number of layers:     13
- Number of macros:     442
- Number of vias:       25
- Number of nets:       191
 
- Total wire length = 3697 um.

I’ve been enjoying solving these problems part of the Hands-on RTL Design course and it is definitely worth the time. Would recommend you check it out!

![Events_To_APB](/events_to_apb_submit.png)
