1
Events to APB
NOT SUBMITTED

Sam is a fan of the AMBA APB protocol and has taken up the challenge to design a block which converts certain input events to APB transactions. The design takes three different inputs and generates an APB transaction to a single slave. Whenever any input is asserted, Sam wants to send out an APB transaction to an address reserved for the particular event. Sam needs your help to design the events to APB converter.

All the flops (if any) should be positive edge triggered with asynchronous resets.

Interface Definition

  • The block takes three single bit inputs:
    event_a_i
    event_b_i
    event_c_i
  • The output APB transaction uses the following signals:
    apb_psel_o
    apb_penable_o
    apb_paddr_o[31:0]
    apb_pwrite_o
    apb_pwdata_o[31:0]
    apb_pready_i
    The APB transaction should be generated whenever any of the input event is asserted. The generated APB transactions should always be an APB write transaction. Hence the interface doesn't contain the apb_prdata_i input.

eventsToAPB_block_diagram

Interface Requirements

  • The APB transaction must comply with the AMBA APB protocol specifications
  • The three event inputs are mutually exclusive i.e. there can be atmost one event asserted on a cycle
  • The APB transaction generated due to Event A should be sent to address 0xABBA0000
  • The APB transaction generated due to Event B should be sent to address 0xBAFF0000
  • The APB transaction generated due to Event C should be sent to address 0xCAFE0000
  • The write data should give the count of the number of events seen since the last write for that particular event
  • The APB interface guarantees that the pready signal would be asserted within 10 cycles for a particular transaction without any pslverr. Hence the interface doesn't contain the pslverr input
  • Back to back APB transactions aren't supported by interface hence there should a cycle gap before the next APB transaction is generated
  • The event input interface guarantees fairness amongst the three events such that there cannot be more than 10 pending events for any input event

Note: The above fairness scheme allows you to implement the address selection logic for the APB request in any given order of priority for the inputs.

Sample Simulation

events_To_APB

initializing...

Code editor is disabled. Please use desktop version of the site for a better hands on experience.

Sam is a fan of the AMBA APB protocol and has taken up the challenge to design a block which converts certain input events to APB transactions. The design takes three different inputs and generates an APB transaction to a single slave. Whenever any input is asserted, Sam wants to send out an APB transaction to an address reserved for the particular event. Sam needs your help to design the events to APB converter.

All the flops (if any) should be positive edge triggered with asynchronous resets.

Interface Definition

  • The block takes three single bit inputs:
    event_a_i
    event_b_i
    event_c_i
  • The output APB transaction uses the following signals:
    apb_psel_o
    apb_penable_o
    apb_paddr_o[31:0]
    apb_pwrite_o
    apb_pwdata_o[31:0]
    apb_pready_i
    The APB transaction should be generated whenever any of the input event is asserted. The generated APB transactions should always be an APB write transaction. Hence the interface doesn't contain the apb_prdata_i input.

eventsToAPB_block_diagram

Interface Requirements

  • The APB transaction must comply with the AMBA APB protocol specifications
  • The three event inputs are mutually exclusive i.e. there can be atmost one event asserted on a cycle
  • The APB transaction generated due to Event A should be sent to address 0xABBA0000
  • The APB transaction generated due to Event B should be sent to address 0xBAFF0000
  • The APB transaction generated due to Event C should be sent to address 0xCAFE0000
  • The write data should give the count of the number of events seen since the last write for that particular event
  • The APB interface guarantees that the pready signal would be asserted within 10 cycles for a particular transaction without any pslverr. Hence the interface doesn't contain the pslverr input
  • Back to back APB transactions aren't supported by interface hence there should a cycle gap before the next APB transaction is generated
  • The event input interface guarantees fairness amongst the three events such that there cannot be more than 10 pending events for any input event

Note: The above fairness scheme allows you to implement the address selection logic for the APB request in any given order of priority for the inputs.

Sample Simulation

events_To_APB