Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

## Introduction
In this PPA challenge, you are responsible for fixing the timing path on the find first one-hot
output vector of the given module. The find first module is designed to have N requests and the
module gives the one-hot output vector indicating the first request that is asserted.

The boilerplate code for the module is provided to you and you need to modify the code to fix the
timing path on the output. You can use any technique to fix the timing path such as
pipelining the output data or using a different architecture for the module. The only requirement
is that the module should be functional and should meet the interface requirements mentioned below.

All the flops should be positive edge triggered with active high resets (if any).

## Interface Definition

```verilog
NUM_PORTS   => The number of requests that the module can handle

req_i       => The input request vector of size NUM_PORTS
first_set_o => The output one-hot vector indicating the first request that is asserted
```

## Interface Requirements
- The module should take in a request vector of size NUM_PORTS and output a one-hot vector of the same size indicating the first request that is asserted
- The output should be valid in the same cycle as the input request vector is asserted
- The output should be zero if no requests are asserted in the input vector
- The module should be designed to handle any number of requests up to NUM_PORTS
