Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

## Introduction
In this PPA challenge, you are responsible for fixing the timing path on the pop data
output of a first-in first-out buffer (fifo). The fifo is designed to have N entries and each
entry is DATA_W wide. The fifo has the standard push and pop interface along with the full
and empty flags.

The boilerplate code for the fifo is provided to you and you need to modify the code to fix the
timing path on the pop data output. You can use any technique to fix the timing path such as
pipelining the output data or using a different architecture for the fifo. The only requirement
is that the fifo should maintain the first-in first-out order and should meet the interface
requirements mentioned below.

All the flops should be positive edge triggered with active high resets (if any).

## Interface Definition

```verilog
N           => A parameter N for the number of entries in the fifo
DATA_W      => The parameter for the data width of each entry in the fifo

push_i      => Input signal to push into the fifo
push_data_i => Input to the module which gives the push data

pop_i       => Input signal to pop from the fifo
pop_data_o  => The output popped data from the fifo

empty_o     => The output empty flag
full_o      => The output full flag
```

## Interface Requirements
- The fifo should maintain the first-in first-out order of the data
- The push and pop operations should be independent of each other, meaning that the fifo should be able to push and pop data in the same cycle if both push_i and pop_i are asserted
- The empty flag should be asserted when the fifo is empty and deasserted when there is at least one entry in the fifo
- The full flag should be asserted when the fifo is full and deasserted when there is at least one empty entry in the fifo
- The pop data output should be valid in the same cycle when pop_i is asserted and there is at least one entry in the fifo to pop
- The push_i signal will only be asserted when the fifo is not full
- The pop_i signal will only be asserted when the fifo is not empty


```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Fast Fifo - RTL
// --------------------------------------------------------
module fast_fifo #(
  parameter N = 32,
  parameter DATA_W = 4
)(
  input   logic               clk,
  input   logic               reset,

  input   logic               push_i,
  input   logic [DATA_W-1:0]  push_data_i,

  input   logic               pop_i,
  output  logic [DATA_W-1:0]  pop_data_o,

  output  logic               empty_o,
  output  logic               full_o
);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  logic [DATA_W-1:0]            pop_data;
  logic [DATA_W-1:0]            pop_data_q;
  logic [DATA_W-1:0]            nxt_pop_data;
  logic                         pop_data_en;

  logic                         pop_buffer_valid_q;
  logic                         nxt_pop_buffer_valid;

  logic                         fifo_push_en;
  logic                         fifo_pop_en;
  logic                         push_to_pop_buffer;

  logic                         empty;
  logic                         full;

  // --------------------------------------------------------
  // Flops for the pop data buffer and its valid bit
  // --------------------------------------------------------
  assign pop_data_en = (~pop_buffer_valid_q & push_i) | pop_i;
  assign nxt_pop_data = empty ? push_data_i : pop_data;
  always_ff @(posedge clk)
    if (pop_data_en)
      pop_data_q <= nxt_pop_data;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      pop_buffer_valid_q <= 1'b0;
    else if (push_i | pop_i)
      pop_buffer_valid_q <= nxt_pop_buffer_valid;
  
  assign nxt_pop_buffer_valid = (push_i | ~empty) |
                                (pop_buffer_valid_q & ~pop_i);

  assign push_to_pop_buffer = push_i & ((~pop_buffer_valid_q) | (pop_i & empty));

  assign fifo_push_en = push_i & ~push_to_pop_buffer;
  assign fifo_pop_en  = pop_i & ~empty;

  // --------------------------------------------------------
  // Instantiate the internal fifo
  // --------------------------------------------------------
  qs_fifo #(
    .DEPTH(N-1),
    .DATA_W(DATA_W)
  ) u_fifo (
    .clk          (clk),
    .reset        (reset),
    .push_i       (fifo_push_en),
    .push_data_i  (push_data_i),
    .pop_i        (fifo_pop_en),
    .pop_data_o   (pop_data),
    .empty_o      (empty),
    .full_o       (full)
  );

  // --------------------------------------------------------
  // Output Assignments
  // --------------------------------------------------------
  assign full_o     = full;
  assign empty_o    = empty & ~pop_buffer_valid_q;
  assign pop_data_o = pop_data_q;

endmodule

```
