Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Design a [Least Recently Used]([https://en.wikipedia.org/wiki/Cache_replacement_policies#Least_recently_used_(LRU)]) module for a N-way set associative cache. The number of ways for the
cache are parameterized but will always be a power of 2. 

All the flops (if any) should be positive edge triggered with asynchronous resets.

## Interface Definition

```verilog
ls_valid_i → Indicates a valid operation
ls_op_i    → Operation type: can be either read, write or an invalidation operation
ls_way_i   → Gives the way information for read and invalidation operation

lru_valid_o      → The output way information is valid on this cycle
lru_way_o[N-1:0] → The one-hot decoded way for the current operation
```

