1
LRU
NOT SUBMITTED
Design a Least Recently Used module for a N-way set associative cache. The number of ways for the cache are parameterized but will always be a power of 2.
All the flops (if any) should be positive edge triggered with asynchronous resets.
Interface Definition
ls_valid_i → Indicates a valid operation
ls_op_i → Operation type: can be either read, write or an invalidation operation
ls_way_i → Gives the way information for read and invalidation operation
lru_valid_o → The output way information is valid on this cycle
lru_way_o[N-1:0] → The one-hot decoded way for the current operation.lennahc drocsid ruo no su ot tuo hcaer ro su llac esaelp ,stbuod evah llits uoy fI .melborp siht fo tnetnoc lautca eht ees ot ebircsbus esaelP
?siht daer ot uoy detnaw ew kniht uoy oD !gnizama era uoy ,txet siht daer ot elba era uoy fI .uoy pleh ot yppah eb lliw eW
?od nac ew erom tahw ,evorpmi nac ew woh wonk su teL !gnizama ,sey fI ?siht daer ot elba uoy ereW
!uoy ta kcab evaw yletinifed ot evol dluow eW !iH yas ot tsuj su ot tuo hcaer syawla nac uoY !sklof yldneirf era ew ,oslA
!reffo ot evah ew tahw ekil ot gniog era uoy erus era eW .gnibircsbus erofeb deirt eb nac dna elbaliava yleerf era hcihw seludom wef a era ereht ,syawynA
!daeha efil gnizama na dna yad taerg a evaH
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Emacs
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System Verilog
Verilog
VHDL
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY