1
Low Power Channel
NOT SUBMITTED
Design a module which integrates the ARM Q-channel protocol for managing power transitions.
Interface Definition
if_wakeup_i → Wakeup request from the upstream
wr_valid_i → A valid write to the fifo
wr_payload_i → Write data associated with the valid write
wr_flush_o → Flush signal to indicate upstream to flush all the writes
wr_done_i → All pending writes completed by upstream
rd_valid_i → Read valid to the internal fifo
rd_payload_o → Output payload on this read
qreqn_i → Active low QREQn signal
qacceptn_o → Active low QACCEPTn signal
qactive_o → Active high QACTIVE signal
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Emacs
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System Verilog
Verilog
VHDL
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY