Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Design a module which integrates the ARM Q-channel protocol for managing power transitions. 

## Interface Definition

```verilog
if_wakeup_i → Wakeup request from the upstream
```

```verilog
wr_valid_i   → A valid write to the fifo
wr_payload_i → Write data associated with the valid write
```

```verilog
wr_flush_o → Flush signal to indicate upstream to flush all the writes
wr_done_i  → All pending writes completed by upstream
```

```verilog
rd_valid_i   → Read valid to the internal fifo
rd_payload_o → Output payload on this read
```

```verilog
qreqn_i     → Active low QREQn signal
qacceptn_o  → Active low QACCEPTn signal
qactive_o   → Active high QACTIVE signal
```



I spent some time solving the Low Power Channel problem on QuickSilicon.in

This was an interesting RTL Design problem which involved integrating the AMBA Q-channel protocol with a transaction buffer for a low power design. Here are a few more details from synthesizing my design:

- Number of layers:     13
- Number of macros:     442
- Number of vias:       25
- Number of nets:       262

- Total wire length = 6238 um.

I’ve been enjoying solving these problems part of the Hands-on RTL Design course and it is definitely worth the time. Would recommend you check it out!

![Low_Power_Channel](/low_power_channel_submit.png)
