Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Multi Pop Fifo

Write Coalescing

Fifo ID Tracker

## Introduction
In this PPA challenge, you are given a first-in first-out buffer (fifo) that takes one push per
cycle but can pop up to NUM_POP entries in a single cycle. The NUM_POP oldest entries are
always shown on the pop lanes: lane 0 is the oldest entry, lane 1 the next oldest, and so on.
Each cycle, `pop_therm_i` says which of them are taken. It is thermometer encoded: bit i pops
lane i, and the set bits always start from lane 0, so popping n entries sets the n lowest bits.

For example, with entries A (oldest), B, C, D and E in the fifo and NUM_POP = 4, the lanes show
A, B, C and D. `pop_therm_i = 4'b0111` pops 3 entries and leaves D and E, so the next cycle the
lanes show D and E with lanes 2 and 3 not valid.

The boilerplate code works but is slow: for every lane it adds the lane number to the read
pointer, wraps it, and reads that slot out of the whole storage. Your task is to keep the same
behaviour while improving the timing and area of the design. The synthesis and timing report
after each run shows how your design compares with the reference solution.

All the flops should be positive edge triggered with active high resets (if any).

## Interface Definition

```verilog
DEPTH        => Number of entries in the fifo
DATA_W       => Width of each entry
NUM_POP      => Number of pop lanes: the most entries that can be popped in a cycle

push_i       => Push an entry into the fifo
push_data_i  => The entry to push

pop_therm_i  => Thermometer-encoded pop: bit i pops lane i (e.g. 4'b0011 pops the 2 oldest)
pop_data_o   => pop_data_o[i] is the i-th oldest entry (lane 0 is the oldest)
pop_valid_o  => pop_valid_o[i] is high when the fifo holds at least i+1 entries

count_o      => Number of entries currently in the fifo
```

## Interface Requirements
- The fifo must keep entries in first-in first-out order
- Push and pop can happen in the same cycle
- `pop_data_o` and `pop_valid_o` must reflect the entries stored at the start of the cycle;
  `pop_data_o[i]` is only checked when `pop_valid_o[i]` is high
- `count_o` must reflect the entries stored at the start of the cycle (it updates the cycle
  after a push or pop)
- `pop_therm_i` is always a thermometer code: all ones from bit 0 up, then all zeros
  (`4'b0000`, `4'b0001`, `4'b0011`, `4'b0111` or `4'b1111` for NUM_POP = 4)
- `pop_therm_i` only pops lanes that are valid: it never has more bits set than there are
  entries in the fifo
- `push_i` will only be asserted when there's room for the entry (counting the entries popped
  in the same cycle)


```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Multi-Pop Fifo - RTL
// --------------------------------------------------------
// A fifo that takes one push per cycle and pops up to NUM_POP entries per
// cycle. pop_data_o[i] always shows the i-th oldest entry (lane 0 is the
// oldest) and pop_valid_o[i] says whether that lane holds an entry;
// pop_therm_i is thermometer coded and pops one oldest entry per set bit.
//
// Banked version: entries are written round-robin into NUM_POP qs_fast_fifo
// banks, so the NUM_POP oldest entries sit at the heads of the banks. The
// lanes are those heads rotated by the bank read pointer, and pop_therm_i is
// rotated the same way to pop the right banks.
module multi_pop_fifo #(
  parameter DEPTH   = 16,
  parameter DATA_W  = 16,
  parameter NUM_POP = 4,
  localparam CNT_W  = $clog2(DEPTH + 1)
)(
  input   logic                             clk,
  input   logic                             reset,

  input   logic                             push_i,
  input   logic [DATA_W-1:0]                push_data_i,

  input   logic [NUM_POP-1:0]               pop_therm_i,
  output  logic [NUM_POP-1:0][DATA_W-1:0]   pop_data_o,
  output  logic [NUM_POP-1:0]               pop_valid_o,

  output  logic [CNT_W-1:0]                 count_o
);

  localparam NUM_BANKS = NUM_POP;
  localparam BANK_DEPTH = DEPTH / NUM_BANKS;
  localparam NUM_BANK_W = $clog2(NUM_BANKS);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  logic [CNT_W-1:0]                       count_q;
  logic [CNT_W-1:0]                       nxt_count;
  logic [$clog2(NUM_POP+1)-1:0]           pop_cnt;
  logic [NUM_BANK_W-1:0][NUM_POP-1:0]     pop_rotate;
  logic [NUM_BANKS-1:0][DATA_W-1:0]       pop_data_concat;
  logic [NUM_BANKS-1:0][DATA_W-1:0]       pop_data;
  logic [NUM_BANKS-1:0]                   push;
  logic [NUM_BANKS-1:0]                   pop;
  logic [NUM_BANK_W-1:0]                  nxt_bank_rd;
  logic [NUM_BANK_W-1:0]                  bank_rd_q;
  logic [NUM_BANK_W-1:0]                  nxt_bank_wr;
  logic [NUM_BANK_W-1:0]                  bank_wr_q;
  // The banks' own flags aren't needed: count_q tracks occupancy across banks
  /* verilator lint_off UNUSEDSIGNAL */
  logic [NUM_BANKS-1:0]                   bank_empty;
  logic [NUM_BANKS-1:0]                   bank_full;
  /* verilator lint_on UNUSEDSIGNAL */

  // --------------------------------------------------------
  // Banked Fifo
  // --------------------------------------------------------
  for (genvar i=0; i<NUM_BANKS; i++) begin : g_fifo_bank
    assign push[i] = push_i & bank_wr_q == i;
    assign pop[i] = pop_rotate[$clog2(NUM_POP)-1][i];
    qs_fast_fifo #(.N(BANK_DEPTH), .DATA_W(DATA_W)) u_fifo_bank (
      .clk            (clk),
      .reset          (reset),
      .push_i         (push[i]),
      .push_data_i    (push_data_i),
      .pop_i          (pop[i]),
      .pop_data_o     (pop_data[i]),
      .empty_o        (bank_empty[i]),
      .full_o         (bank_full[i])
    );
  end

  // --------------------------------------------------------
  // Fifo Count
  // --------------------------------------------------------
  always_ff @(posedge clk or posedge reset)
    if (reset) begin
      count_q  <= CNT_W'(1'b0);
    end else begin
      count_q  <= nxt_count;
    end
  assign nxt_count  = count_q + CNT_W'(push_i) - CNT_W'(pop_cnt);

  qs_pop_cnt #(.N(NUM_POP)) pop_cnt_w (
    .clk            (clk),
    .reset          (reset),
    .req_i          (pop_therm_i),
    .pop_cnt_o      (pop_cnt)
  );

  always_ff @(posedge clk or posedge reset)
    if (reset) begin
      bank_rd_q  <= NUM_BANK_W'(1'b0);
      bank_wr_q  <= NUM_BANK_W'(1'b0);
    end else begin
      bank_rd_q  <= nxt_bank_rd;
      bank_wr_q  <= nxt_bank_wr;
    end
  assign nxt_bank_rd = bank_rd_q + NUM_BANK_W'(pop_cnt);
  assign nxt_bank_wr = bank_wr_q + NUM_BANK_W'(push_i);

  // Align pop_term_i with the bank count to ensure we pop
  // the correct number of entries from the fifo banks
  for (genvar i=0; i<NUM_BANK_W; i++) begin : g_pop_therm_rotate
    if (i==0)
      assign pop_rotate[i] = bank_rd_q[i] ? {pop_therm_i[NUM_POP-1-(i+1):0], pop_therm_i[NUM_POP-1]} : pop_therm_i;
    else
      assign pop_rotate[i] = bank_rd_q[i] ? {pop_rotate[i-1][NUM_POP-1-(i+1):0], pop_rotate[i-1][NUM_POP-1:i+1]} : pop_rotate[i-1];
  end

  // Mux out the pop data based on the current count value
  assign pop_data_concat = (NUM_BANKS*DATA_W)'({pop_data, pop_data} >> bank_rd_q * DATA_W);

  // --------------------------------------------------------
  // Output Assignments
  // --------------------------------------------------------
  always_comb begin
    for (int i = 0; i < NUM_POP; i++) begin
      pop_data_o[i]  = pop_data_concat[i];
      pop_valid_o[i] = i < int'(count_q);
    end
  end

  assign count_o = count_q;

endmodule
```
