Sequential Design
FIFO (First-In-First-Out)
A buffer that stores data elements and retrieves them in the order they were written.
Detailed Explanation
FIFOs decouple producers from consumers, absorbing rate variations. They use circular memory with read and write pointers. Empty and full conditions are detected by comparing pointers—equal pointers with matching wrap flags mean empty; equal pointers with different wrap flags mean full.
Synchronous FIFOs have one clock domain. Asynchronous FIFOs cross clock domains, using gray-coded pointers for safe CDC. FIFO depth is chosen based on rate differences and acceptable backpressure.
Code Example
systemverilog
// Synchronous FIFO pointers and flags
logic [PTR_W-1:0] rd_ptr_q, wr_ptr_q;
logic rd_wrap_q, wr_wrap_q;
assign empty = (rd_ptr_q == wr_ptr_q) && (rd_wrap_q == wr_wrap_q);
assign full = (rd_ptr_q == wr_ptr_q) && (rd_wrap_q != wr_wrap_q);
// Write pointer update
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr_q <= '0;
wr_wrap_q <= 1'b0;
end else if (wr_en && !full) begin
if (wr_ptr_q == DEPTH-1) begin
wr_ptr_q <= '0;
wr_wrap_q <= ~wr_wrap_q;
end else begin
wr_ptr_q <= wr_ptr_q + 1'b1;
end
end
end