Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Quite often your logic needs to react to a change on some control signal. That can be an external
input, something saying that another part of the circuit has done it's job and that it is safe to
continue. All sorts of scenarios exist that call for a signal generated by one part of a system to
be detected by another part or a different system.

Implement a one-shot circuit which detects a pos-edge (from 0-1) change on the input.
All the flops (if any) should be positive edge triggered with asynchronous resets.

## Interface Definition

```
data_i : Input signal to the circuit
shot_o : Output signal which detects a positive edge on the input
```

