You are tasked to design a module which buffers requests between the incoming valid-ready based RX interface and the outgoing valid-ready based TX interface. Each requests on the RX interface can only be given out on the TX interface once it has retired and has met its ordering constraints. The buffer must be wide enough to hold exactly 8 requests.
The requests on the RX interface can have no ordering constraints (unordered requests) which implies that those requests may be given out on the TX interface as soon as those are retired. Whereas certain requests can have a strict ordering requirement (ordered requests) where the request can be only be given out if all of the earlier pending requests seen on the RX interface have been given out on the TX interface.
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