Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

You are tasked to design a module which buffers requests between the incoming valid-ready based RX
interface and the outgoing valid-ready based TX interface. Each requests on the RX interface can only
be given out on the TX interface once it has retired and has met its ordering constraints. The buffer
must be wide enough to hold exactly 8 requests.

The requests on the RX interface can have no ordering constraints (unordered requests) which implies
that those requests may be given out on the TX interface as soon as those are retired. Whereas certain
requests can have a strict ordering requirement (ordered requests) where the request can be only be
given out if all of the earlier pending requests seen on the RX interface have been given out on the
TX interface. 




I spent some time solving the Ordering problem on QuickSilicon.in

This was an interesting RTL Design problem which involved designing a buffer with relative age ordering support to handle out-of-order transactions. Here are a few more details from synthesizing my design:

- Number of layers:     13
- Number of macros:     442
- Number of vias:       25
- Number of nets:       867

- Total wire length = 28304 um.

I’ve been enjoying solving these problems part of the Hands-on RTL Design course and it is definitely worth the time. Would recommend you check it out!

![Ordering_Submit](/ordering_submit.png)
