Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

You are working on the next generation Processor unit and are responsible for designing
the CPU performance monitor extension. The performance monitors usually contains a fixed number
of counters which can be programmed to be triggered on an event from different CPU units.

Design the base counter module which can be instantiated depending on the implemented number of
such counter in the CPU. The counter should be triggered on a single-bit event received from the
CPU pipeline. The counter output should only be accessible to software reads and thus has a software
read request as an input.



Perf Counters