Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Design the following sequence generator module:

0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → ...

Assume the sequence goes on forever until the circuit is reset.
All the flops should be positive edge triggered with asynchronous resets (if any).

## Interface Definition

```
seq_o : Sequence output on every cycle
```

## Interface Requirements
- The generator should produce output every cycle
- You can assume that the sequence generator would never overflow


Design the following sequence generator module:

0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → ...

## Interface Definition

```
seq_o : Sequence output on every cycle
```

## Interface Requirements
- The generator should produce output every cycle
- You can assume that the sequence generator would never overflow



## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Sequence Generator - RTL
// --------------------------------------------------------

module seq_generator (
  input   wire        clk,
  input   wire        reset,

  output  wire [31:0] seq_o
);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  logic [31:0] seq_t0;
  logic [31:0] seq_t1;
  logic [31:0] seq_t2;

  logic [31:0] seq_nxt;

  always_ff @(posedge clk or posedge reset)
    if (reset) begin
      seq_t0 <= 32'h1;
      seq_t1 <= 32'h1;
      seq_t2 <= 32'h0;
    end else begin
      seq_t0 <= seq_nxt[31:0];
      seq_t1 <= seq_t0[31:0];
      seq_t2 <= seq_t1[31:0];
    end

  assign seq_nxt[31:0] = {seq_t1[31:0]} + {seq_t2[31:0]};

  // -------------------------------------------------------
  // Output assignments
  // --------------------------------------------------------
  assign seq_o[31:0] = seq_t2[31:0];

endmodule
```

-----------
## Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Sequence Generator - RTL
// --------------------------------------------------------

module seq_generator (
  input   wire        clk,
  input   wire        reset,

  output  wire [31:0] seq_o
);

  // --------------------------------------------------------
  // Internal wire and regs
  // --------------------------------------------------------
  reg [31:0] seq_t0;
  reg [31:0] seq_t1;
  reg [31:0] seq_t2;

  wire [31:0] seq_nxt;

  always @(posedge clk or posedge reset)
    if (reset) begin
      seq_t0 <= 32'h1;
      seq_t1 <= 32'h1;
      seq_t2 <= 32'h0;
    end else begin
      seq_t0 <= seq_nxt[31:0];
      seq_t1 <= seq_t0[31:0];
      seq_t2 <= seq_t1[31:0];
    end

  assign seq_nxt[31:0] = {seq_t1[31:0]} + {seq_t2[31:0]};

  // -------------------------------------------------------
  // Output assignments
  // --------------------------------------------------------
  assign seq_o[31:0] = seq_t2[31:0];

endmodule
```

-----------
## VHDL

```vhdl
-- --------------------------------------------------------
-- Copyright (C) quicksilicon.io - All Rights Reserved
--
-- Unauthorized copying of this file, via any medium is
-- strictly prohibited
-- Proprietary and confidential
-- --------------------------------------------------------

-- --------------------------------------------------------
-- Sequence Generator - RTL
-- --------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seq_generator is
  port (
  clk   : in  std_logic;
  reset : in  std_logic;

  seq_o : out std_logic_vector(31 downto 0)
  );
end seq_generator;

  -- --------------------------------------------------------
  -- Internal wire and regs
  -- --------------------------------------------------------
  architecture logic of seq_generator is
  signal seq_t0 : unsigned(31 downto 0);
  signal seq_t1 : unsigned(31 downto 0);
  signal seq_t2 : unsigned(31 downto 0);

  signal seq_nxt : unsigned(31 downto 0);

  begin

    process (clk, reset) is
    begin
      if reset = '1' then
        seq_t0 <= to_unsigned(1, 32);
        seq_t1 <= to_unsigned(1, 32);
        seq_t2 <= to_unsigned(0, 32);
      elsif rising_edge(clk) then
        seq_t0 <= seq_nxt;
        seq_t1 <= seq_t0;
        seq_t2 <= seq_t1;
      end if;
    end process;

    seq_nxt <= unsigned(seq_t1) + unsigned(seq_t2);

  -- -------------------------------------------------------
  -- Output assignments
  -- --------------------------------------------------------
    seq_o <= std_logic_vector(seq_t2);

  end architecture;
```
