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Sequence Generator
NOT SUBMITTED
Design the following sequence generator module:
0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → ...
Assume the sequence goes on forever until the circuit is reset. All the flops should be positive edge triggered with asynchronous resets (if any).
Interface Definition
seq_o : Sequence output on every cycleInterface Requirements
- The generator should produce output every cycle
- You can assume that the sequence generator would never overflow
Sublime
Emacs
Sublime
Vim
System Verilog
Verilog
VHDL
initializing...
Modules1. Atomic Counters
EASY
2. Divide by 3 EASY
3. 3-bit Palindrome EASY
4. Sequence Generator EASY
5. Single Cycle Arbiters EASY
6. Events to APB MEDIUM
7. Low Power Channel HARD
8. Two Pulses MEDIUM
9. Clock Generator EASY
10. Skid Buffer HARD
11. Least Recently Used HARD
12. Edge Capture EASY
13. One Shot EASY
14. Parallel to Serial MEDIUM
15. Running Average MEDIUM
16. Big Endian Converter EASY
17. Credits & Deadlock HARD
18. Ordering HARD
19. Performance Counter EASY
20. Asynchronous Resets MEDIUM
21. Fifo Flush HARD
22. Buffering HARD
23. Compression Engine MEDIUM
24. Perfect Squares MEDIUM
25. Cross correlation EASY
26. System Verilog for Design EASY