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Intro to System Verilog for Design
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System Verilog for Design

Welcome to the introductory lesson on using System Verilog for Design. Through the series of videos you would get to learn about various System Verilog constructs and using them to create complex digital circuits.

This video discusses about the two fundamental components that together build up digital circuits:

  • Sequential Logic (Memory element)
  • Combinational Logic (Bunch of gates put together)

It also covers how the hardware description language help describe both the sequential logic and as well as the combinational logic to achieve the desired output.

This video also introduces you to the module keyword along with the input and output ports. It also touches upon the 4-state data-type i.e. the logic datatype which describes the various signals in the block. The 4-states of the data-type can either be:

  • 1 : Logic High
  • 0 : Logic Low
  • X : Unknown
  • Z : High Impedance (disconnected)

The next video discusses about writing RTL for a simple 2:1 mux along with the testbench to test the implementation.

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System Verilog for Design

Welcome to the introductory lesson on using System Verilog for Design. Through the series of videos you would get to learn about various System Verilog constructs and using them to create complex digital circuits.

This video discusses about the two fundamental components that together build up digital circuits:

  • Sequential Logic (Memory element)
  • Combinational Logic (Bunch of gates put together)

It also covers how the hardware description language help describe both the sequential logic and as well as the combinational logic to achieve the desired output.

This video also introduces you to the module keyword along with the input and output ports. It also touches upon the 4-state data-type i.e. the logic datatype which describes the various signals in the block. The 4-states of the data-type can either be:

  • 1 : Logic High
  • 0 : Logic Low
  • X : Unknown
  • Z : High Impedance (disconnected)

The next video discusses about writing RTL for a simple 2:1 mux along with the testbench to test the implementation.