Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

# System Verilog for Design

Welcome to the introductory lesson on using System Verilog for Design. Through the series of videos
you would get to learn about various System Verilog constructs and using them to create complex
digital circuits.

This video discusses about the two fundamental components that together build up digital circuits:
  - Sequential Logic (Memory element)
  - Combinational Logic (Bunch of gates put together)

It also covers how the hardware description language help describe both the sequential logic
and as well as the combinational logic to achieve the desired output.

This video also introduces you to the `module` keyword along with the `input` and `output` ports.
It also touches upon the 4-state data-type i.e. the `logic` datatype which describes the various
signals in the block. The 4-states of the data-type can either be:
  - 1 : Logic High
  - 0 : Logic Low
  - X : Unknown
  - Z : High Impedance (disconnected)

The next video discusses about writing RTL for a simple 2:1 mux along with the testbench to test
the implementation.


## System Verilog for Design - Introduction


Welcome to the introductory lesson on using System Verilog for Design. Through the series of videos
you would get to learn about various System Verilog constructs and using them to create complex
digital circuits.

This video discusses about the two fundamental components that together build up digital circuits:
  - Sequential Logic (Memory element)
  - Combinational Logic (Bunch of gates put together)

It also covers how the hardware description language help describe both the sequential logic
and as well as the combinational logic to achieve the desired output.

This video also introduces you to the `module` keyword along with the `input` and `output` ports.
It also touches upon the 4-state data-type i.e. the `logic` datatype which describes the various
signals in the block. The 4-states of the data-type can either be:
  - 1 : Logic High
  - 0 : Logic Low
  - X : Unknown
  - Z : High Impedance (disconnected)

The next video discusses about writing RTL for a simple 2:1 mux along with the testbench to test
the implementation.



Intro to System Verilog for Design

A simple 2:1 mux is the hardware equivalent for the Hello World program. This example
shows how to implement a 2:1 mux from scratch using System Verilog.

## Interface Definition
`a`   : First input to the mux
`b`   : Second input to the mux
`sel` : Mux select line
`y`   : Mux output

## Note
Please use System Verilog as the selected language. The support for other languages might be broken.


## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Mux - RTL
// --------------------------------------------------------

module mux2to1 (
  input   logic a,
  input   logic b,
  input   logic sel,
  output  logic y
);

  // sel == 0 -> y = a
  // sel == 1 -> y = b
  assign y = sel ? b : a;

endmodule

```

-----------
## Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Mux - RTL
// --------------------------------------------------------

module mux2to1 (
  input   wire a,
  input   wire b,
  input   wire sel,
  output  wire y
);

  // sel == 0 -> y = a
  // sel == 1 -> y = b
  assign y = sel ? b : a;

endmodule

```

-----------
## VHDL

```vhdl
-- --------------------------------------------------------
-- Copyright (C) quicksilicon.io - All Rights Reserved
--
-- Unauthorized copying of this file, via any medium is
-- strictly prohibited
-- Proprietary and confidential
-- --------------------------------------------------------
--
-- --------------------------------------------------------
-- Mux - RTL
-- --------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux2to1 is
  port (
    a   : in  std_logic;
    b   : in  std_logic;
    sel : in  std_logic;

    y   : out std_logic
  );
end mux2to1;

  -- --------------------------------------------------------
  -- Internal wire and regs
  -- --------------------------------------------------------
  architecture logic of mux2to1 is

    begin
      y <= a when sel = '0' else b;

  end architecture;
```


A Simple 2:1 Mux

# System Verilog for Design - Combinational Logic

The last few videos discusses about the two fundamental components that together build up digital circuits:
  - Sequential Logic (Memory element)
  - Combinational Logic (Bunch of gates put together)

This video explains the combinational logic. It also covers the `always_comb` keyword and as well as the `assign`
keyword to build-up complex combinational logic.

This video also introduces you to the continuous assignment and prodcedural assignments in Sytem Verilog.

The next video discusses about writing RTL for sequential circuits.


System Verilog for Design - Combinational Logic

# System Verilog for Design - Sequential Logic

The last few videos discusses about the two fundamental components that together build up digital circuits:
  - Sequential Logic (Memory element)
  - Combinational Logic (Bunch of gates put together)

This video explains the sequential logic and the usage of `clk` signal in designing sequential circuits.
It also covers the `always_ff` keyword in detail.

This video also introduces various flavours of a D flip-flop:
- Non resettable flops
- Flops with synchronous resets
- Flops with asynchronous resets

The next video discusses about using System Verilog for developing a D flip-flop.


System Verilog for Design - Sequential Logic

We have discussed about the basic building blocks of any complex digital ciruits:
- Combinational Logic
- Sequential Logic

This video discusses about the most widely used sequential element i.e. D flip-flop.

We would be designing the three different falvours of a D flip-flop:
- Non resettable
- Synchronous Reset
- Asynchronous Reset

All the flops should be positive edge triggered with active high resets (if any).

This video also discusses the generated waveforms in detail to explain the flop behaviour.

## Interface Definition

```verilog
d_i           => The input to the flop D-pin
q_norst_o     => Output from the non-resettable flop
q_syncrst_o   => Output from the flop with synchronous reset
q_asyncrst_o  => Output from the flop with asynchronous reset
```


We have discussed about the basic building blocks of any complex digital ciruits:
- Combinational Logic
- Sequential Logic

This video discusses about the most widely used sequential element i.e. D flip-flop.

We would be designing the three different falvours of a D flip-flop:
- Non resettable
- Synchronous Reset
- Asynchronous Reset



## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// DFF - RTL
// --------------------------------------------------------

module dff (
  input   logic        clk,
  input   logic        reset,

  input   logic        d_i,

  output  logic        q_norst_o,
  output  logic        q_syncrst_o,
  output  logic        q_asyncrst_o

);

  // --------------------------------------------------------
  // Main logic
  // --------------------------------------------------------
  // No reset
  always_ff @(posedge clk)
    q_norst_o <= d_i;

  // Sync reset
  always_ff @(posedge clk)
    if (reset)
      q_syncrst_o <= 1'b0;
    else
      q_syncrst_o <= d_i;

  // Async reset
  always_ff @(posedge clk or posedge reset)
    if (reset)
      q_asyncrst_o <= 1'b0;
    else
      q_asyncrst_o <= d_i;

endmodule
```
