Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

Design a circuit which takes in two serial inputs `x_i` and
`y_i` and produces an output `p_o`. The output `p_o` is
asserted whenever a pulse on the `x_i` input is seen provided
there have been exactly two pulses on the serial input `y_i`
on or after the last pulse on `x_i` but before the current pulse.
The output should remain asserted until the next pulse is seen
on the serial input `y_i`...

