Name: SystemVerilog for Design
Price: 29 USD
Availability: InStock

Rahul has worked with companies like ARM and Tenstorrent. He holds a BE (Hons) in Electronics and Instrumentation Engineering from BITS Pilani University.

Senior Staff RTL Design Engineer

Rahul Behl

Introduction

Running Simulations

Combinatorial Logic

Sequential Logic

D Flip-Flop

D Flip-Flop with Enable

Counter

Up-down Counter

Self Reloading Counter

Shift Register

A beginner-friendly course to master the widely accepted industry-standard language for RTL design

SystemVerilog for Design

Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

This flagship course on our website will help you learn RTL Design the right way. It is presented as a set of 26 engaging modules, each covering a different RTL and Microarchitecture Design technique to build your conceptual understanding. 

Hands-on RTL Design

Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

This comprehensive course offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA). Whether you're an aspiring computer architect or a seasoned developer looking to expand your knowledge, this course equips you with essential skills and hands-on experience to understand and design RISC-V based processors from scratch.

RISC-V Processor Design

SystemVerilog Testbench Introduction

SystemVerilog Testbench Architecture

APB Interface

APB Transaction

APB Generator

APB Driver

APB Driver Phase 2

APB Monitor

APB Scoreboard

APB Environment

APB Testbench Top

RISC-V Processor (YARP) Interface

YARP Transaction

YARP Generator

YARP Driver

YARP Data Memory Model

YARP Monitor

YARP Scoreboard

YARP Testbench Top

DVCon 26 Hackathon Problem

Array Sum Limit

Array Index Sum Limit

Ball Draw No Repeat

Conditional Even Probability

Even Odd Index Value

Five Consecutive Ones

Frequency Constraint

Grouped Ones

Index Value Range

Leap Year

Matrix Rotation

Non Adjacent Ones

Power of 4

Dynamic Ranges

Recent Four Unique

Row Max Unique

Subarray Max Sum

Three Duplicates Only

Tic Tac Toe

Unique 3D Array

Weighted Popcount

Unique Sum

Split Array into Queues

Hands-on course to learn SystemVerilog Testbenches. The course would teach you how to build fully functional and modern SystemVerilog based Testbenches. You would be building two fully functional testbenches starting right from Interface Specification all the way to building drivers, scoreboards, monitors and checkers and even integrating DPI calls to verify a RISC-V RV32I Processor!

Hands-on Testbench Design

Senior Hardware Engineer

Sumanth Kalluri

Switching Gears

Gearing Down

Gearter Complexity

Packing Up

Transformations

Threads and Memories

Drop the Garbage

Handling Traffic

Handling Traffic 2

More Statistics

Parser 1

Parser 2

Power Saving

Scatter And Gather

Setting Boundary

Smart Pipelines

Throttle Limits

Wider Range

Counting Time 1

Counting Time 2

checksums

Hands-On RTL design for Networking Systems

VIPT Cache Introduction

VIPT Cache Parameters

SKY130 SRAM Macros

VIPT Cache Data Pipeline

VIPT Cache Replacement Policy

VIPT Cache Tag Pipeline

VIPT Cache Top

This course teaches you how to design and build a 4-way set associative Virtually Indexed, Physically Tagged (VIPT) cache from scratch. The cache is specifically developed as an instruction cache for a RISC-V processor, providing practical, architecture-aligned experience.


VIPT Cache Design

QuickSilicon All Access gives you every live, paid course on the platform under a single subscription. Work through structured RTL design and verification tracks, build and simulate real hardware designs in the browser, and get your work checked automatically with pre-designed testbenches and PPA via synthesis.

Your membership stays current: any new paid course published while your subscription is active is included automatically, at no extra cost. Choose monthly, quarterly, or yearly billing, and cancel renewal at any time while keeping access through the period you have already paid for.

Get every paid QuickSilicon course with one membership. RTL design, verification, testbench design, and processor design, plus every new course as it launches.

QuickSilicon All Access Membership - Every RTL Design and Verification Course

One membership for every paid QuickSilicon course - RTL design, verification, testbench design, and processor design - including new courses as they launch.

QuickSilicon All Access

MasterSystemVerilog for Design

All courses. One membership.

What You'll Master

Ready to Start Your Journey?

Course Overview

Meet Your Instructor

Rahul Behl

Learning Outcomes

Skills You'll Gain

Course Details