In the last video we discussed about the D flip-flop and modelled it with different reset strategies. This video discusses about the enable pin en to the flip-flop. It is important to understand how enable pin can be used to model complex hardware logic involving D flip-flops and also how it can be used to reduce power.

We would be designing the D flip-flop with enable pin with enable pin. All the flops should be positive edge triggered with active high resets (if any).

This video also discusses the generated waveforms in detail to explain the flop behaviour.

Interface Definition

d_i  => The input to the flop D-pin
en_i => The enable input to the flop
q_o  => Output from the flop