APB Monitor

We've implemented the following components for our testbench so far:

• APB Interface with the clocking block
• APB Transaction class which generates random transaction objects for the TB
• APB Generator which helps communicate the generated transaction objects to the driver
• APB Driver which gets the randmized transaction objects and drives it to the DUT pins

In this module we would implement the monitor component. As the name suggests the monitor class is responsible for sampling the DUT outputs, processing those and then sending them to the scoreboard. The monitor class also utilises the virtual interface to access the DUT output pins and then uses a mailbox to communicate with the scoreboard which checks the actual DUT output with the expected value.

Testbench_Architecture

Since the testbench here is used to verify the APB Master system, the monitor would sample all the outputs produced by the DUT i.e.

• apb_psel
• apb_penable
• apb_paddr
• apb_pwrite
• apb_pwdata

In the last module, we saw that an APB transfer is complete when apb_psel, apb_penable and the apb_pready signals are all asserted on the same clock edge. We would utilise the same check here and only put the transaction in the mailbox connecting the monitor and the scoreboard on a valid APB transfer. Doing it this way would simplify the checking mechanism in the scoreboard which we would implement in the next module.