Verification

Monitor

A passive testbench component that observes a DUT interface and reconstructs protocol transactions for logging, coverage, and checking.

Detailed Explanation

A monitor is the eyes of the testbench. It sits on a DUT interface in read-only mode — it never drives pins — and watches signal activity cycle by cycle. When it recognizes the shape of a complete transaction (an APB setup/access pair, an AXI handshake, a packet header + payload) it packages the observed fields into a transaction object and publishes it to downstream components like the scoreboard and coverage collector.

Monitors are the reason a testbench can be interface-correct even when the stimulus is random. They enforce the principle that *checking* is decoupled from *driving* — the same monitor works whether the traffic is directed, constrained-random, or coming from a real software workload. Well-written monitors also emit assertions on protocol invariants so that violations surface instantly, not 10,000 cycles later when the scoreboard eventually disagrees.

Code Example

systemverilog
class apb_monitor;
  virtual apb_if vif;
  mailbox #(apb_txn) out_mbx = new();
  task run();
    apb_txn t;
    forever begin
      @(posedge vif.clk);
      if (vif.psel && vif.penable && vif.pready) begin
        t = new();
        t.addr  = vif.paddr;
        t.data  = vif.pwrite ? vif.pwdata : vif.prdata;
        t.write = vif.pwrite;
        out_mbx.put(t);
      end
    end
  endtask
endclass