MasterHands-on Testbench Design
Hands-on course to learn SystemVerilog Testbenches. The course would teach you how to build fully functional and modern SystemVerilog based Testbenches. You would be building two fully functional testbenches starting right from Interface Specification all the way to building drivers, scoreboards, monitors and checkers and even integrating DPI calls to verify a RISC-V RV32I Processor!
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$58 · 1 year access
What You'll Master
Build the practical skills described in this course
Various SystemVerilog Verification constructs useful for building modern testbenches
20+ Interview style constraint problems
Start from architecture and go all the way up-to transactions, driver and scoreboards
Build complete testbench with DPI support to verify RV32I RISC-V Processor
Get video explanations and working solutions in SystemVerilog
Ready to Start Your Journey?
Explore the course content, track your progress, and get answers to your questions
Course Overview
Everything you need to know about this course
Hands-on course to learn SystemVerilog Testbenches. The course would teach you how to build fully functional and modern SystemVerilog based Testbenches. You would be building two fully functional testbenches starting right from Interface Specification all the way to building drivers, scoreboards, monitors and checkers and even integrating DPI calls to verify a RISC-V RV32I Processor!
Meet Your Instructor
Learn from an industry expert with 10+ years of experience
As a passionate educator, Rahul has trained hundreds of engineers in RTL Design and modern verification methodologies, helping them advance their careers in the semiconductor industry.
• SystemVerilog & UVM Methodology
• Formal Verification and methodologies
• High Performance Processor Design
• Experienced RTL Design and Verification Engineers
• Led design and verification projects with focus on Processor Design
Learning Outcomes
What you'll be able to do after completing this course
Skills You'll Gain
Course Details
The curriculum
What you’ll work on
43 modules across 3 sections. Explore in order, or find the problem you want to solve.
APB Interface
11 modules · 3 free
- EasyFree moduleStart
SystemVerilog Testbench Introduction
Say Hello to SystemVerilog Testbenches!
EasyFree - EasyFree moduleStart
SystemVerilog Testbench Architecture
Anatomy of SystemVerilog Testbenches
EasyFree - EasyFree moduleStart
APB Interface
Understand the DUT Interface
EasyFree - EasyCourse accessPreview
APB Transaction
Constraint Randomization for APB
EasyCourse access - EasyCourse accessPreview
APB Generator
Generating transaction objects
EasyCourse access - EasyCourse accessPreview
APB Driver
Toggling the DUT Interface
EasyCourse access - EasyCourse accessPreview
APB Driver Phase 2
Driving consistent transactions
EasyCourse access - EasyCourse accessPreview
APB Monitor
Spying on the DUT outputs
EasyCourse access - EasyCourse accessPreview
APB Scoreboard
Comparing actual vs expected outputs
EasyCourse access - EasyCourse accessPreview
APB Environment
Wrapping all dynamic components together
EasyCourse access - EasyCourse accessPreview
APB Testbench Top
The Top-level of our APB Testbench
EasyCourse access
YARP RISC-V CPU
8 modules · 1 free
- EasyFree moduleStart
RISC-V Processor (YARP) Interface
Understanding the YARP Interface
EasyFree - EasyCourse accessPreview
YARP Transaction
Generating randomg RV32I Instructions
EasyCourse access - EasyCourse accessPreview
YARP Generator
Generating YARP Transactions
EasyCourse access - EasyCourse accessPreview
YARP Driver
Toggling the YARP Interface
EasyCourse access - EasyCourse accessPreview
YARP Data Memory Model
Understanding the YARP Data Memory Model
EasyCourse access - EasyCourse accessPreview
YARP Monitor
Every Testbench needs a monitor
EasyCourse access - EasyCourse accessPreview
YARP Scoreboard
Using C++ models and DPI for checks!
EasyCourse access - EasyCourse accessPreview
YARP Testbench Top
Putting it all together!
EasyCourse access
Constraints
24 modules · 3 free
- MediumFree moduleStart
DVCon 26 Hackathon Problem
Yet Another Processing Protocol
MediumFree - MediumFree moduleStart
Array Sum Limit
Randomize an array such that the sum of elements is fixed
MediumFree - MediumCourse accessPreview
Array Index Sum Limit
Sum of even and odd indices must be constant
MediumCourse access - MediumCourse accessPreview
Ball Draw No Repeat
Draw N balls such that you get no repeats
MediumCourse access - MediumCourse accessPreview
Conditional Even Probability
Probability of generating number depends on the previous number
MediumCourse access - EasyCourse accessPreview
Even Odd Index Value
Element at an even index must be even, and vice-versa
EasyCourse access - MediumCourse accessPreview
Five Consecutive Ones
Give me array with 5 consecutive ones
MediumCourse access - MediumCourse accessPreview
Frequency Constraint
Each distinct value appears a specific number of times.
MediumCourse access - MediumCourse accessPreview
Grouped Ones
All ones are together!
MediumCourse access - EasyCourse accessPreview
Index Value Range
Each element at index must be within a specific range
EasyCourse access - EasyCourse accessPreview
Leap Year
Generate leap years
EasyCourse access - EasyCourse accessPreview
Matrix Rotation
Generate and rotate by 90
EasyCourse access - EasyCourse accessPreview
Non Adjacent Ones
No two consecutive positions contain 1s.
EasyCourse access - EasyCourse accessPreview
Power of 4
Power of 4 generator
EasyCourse access - MediumCourse accessPreview
Dynamic Ranges
Queue with a dynamic range
MediumCourse access - MediumCourse accessPreview
Recent Four Unique
Last four must be unique
MediumCourse access - MediumCourse accessPreview
Row Max Unique
Each row has a unique maximum value
MediumCourse access - MediumCourse accessPreview
Subarray Max Sum
Sub array sum is fixed
MediumCourse access - MediumCourse accessPreview
Three Duplicates Only
Should have exactly 3 duplicates
MediumCourse access - MediumCourse accessPreview
Tic Tac Toe
Yep, it's in the game
MediumCourse access - EasyCourse accessPreview
Unique 3D Array
Generate a unique 3D array
EasyCourse access - MediumCourse accessPreview
Weighted Popcount
Popcount with weights?
MediumCourse access - MediumCourse accessPreview
Unique Sum
Unique Sum Constraint
MediumCourse access - MediumFree moduleStart
Split Array into Queues
Split an array into 3 queues
MediumFree