Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 9
Design and verify a parameterized binary to gray code converter

## Interface Definition
The module should have the following interface:

```verilog
module day9 #(
  parameter VEC_W = 4
)(
  input     wire[VEC_W-1:0] bin_i,
  output    wire[VEC_W-1:0] gray_o

);
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing
the checks or the testbench code then I'd recommend the [Hands-on RTL Design](https://quicksilicon.in/course/rtl-design/?utm_source=quicksilicon&utm_medium=21DaysofRT&utm_campaign=cross-link) course.
The course contains 25 RTL Design problems to help improve your design skills and comes with a
2-part video solution for every problem.


## RTL
```verilog
// Binary to gray code

module day9 #(
  parameter VEC_W = 4
)(
  input     wire[VEC_W-1:0] bin_i,
  output    wire[VEC_W-1:0] gray_o

);

  assign gray_o[VEC_W-1] = bin_i[VEC_W-1];

  genvar i;
  for (i=VEC_W-2; i>=0; i=i-1)
    assign gray_o[i] = bin_i[i+1] ^ bin_i[i];

endmodule
```
## TB
```verilog
module day9_tb ();

  parameter VEC_W = 5;

  logic [VEC_W-1:0] bin_i;
  logic [VEC_W-1:0] gray_o;

  day9 #(VEC_W) DAY9 (.*);

  initial begin
    for (int i=0; i<2**VEC_W; i=i+1) begin
      bin_i = i;
      #5;
    end
    $finish();
  end

endmodule
```
