YARP Decode

The last tutorial covered how the processor fetches an instruction. Fetching the instruction is the first part and now the processor needs to understand how to decode and execute that instruction. The decode stage is quite important as it is where the instruction encodings would be decoded based on the RISC-V ISA. Decoding an instruction involves a couple of parts and this tutorial would cover those step-by-step. Before going ahead, please download the latest RISC-V ISA from this link as the tutorial would be referencing the ISA for the instruction encodings.

Instruction Decode

Every ISA defines the following for an instruction:

• The length of the instruction (in our RISC-V processor every instruction is 32-bit wide)
• The number of architectural registers instruction can access. These could be either source registers (which specify the data which the instruction would process) or the destination register (where the result of the operation would be stored)
• The operation which the instruction should perform. Add, subtract, shifting, multiplication are different example of these operations
• Few other sideband signals - these would be used to allow the processor to decode these instructions easily All the above information is usually contained within the instruction (this is what the 32-bits of the instruction covers).