Architecture
YARP (Yet Another RISC-V Processor)
An educational RISC-V processor implementation used in QuickSilicon courses to teach processor design fundamentals.
Detailed Explanation
YARP is a pedagogical single-cycle RISC-V processor that implements the RV32I base integer instruction set. It demonstrates fundamental processor concepts: instruction fetch, decode, register file access, ALU execution, memory access, and writeback—all in a single clock cycle.
The single-cycle design simplifies understanding but limits clock frequency (critical path spans the entire instruction execution). YARP serves as a foundation before studying pipelined implementations that overlap instruction phases for higher throughput.