YARP Fetch

This lesson would cover one of the basic building block of the RISC-V processor i.e. the Instruction Memory. But before jumping into the details, here is a quick recap of the previous tutorial. The last tutorial touched upon what an Instruction Set Architecture means and how it defines the various instructions as specified by the architecture. The processors are supposed to fetch, decode and execute those instructions keeping all the rules intact as defined by the ISA. This tutorial would cover the first aspect of the process that is fetching the instructions!

Instruction Fetch

Before the processor can decode or execute an instruction, it needs to fetch (or simply get) the instruction from the memory. The binary encodings of the instructions are stored in the memory and the processor uses the program counter (an address to memory in other words) to read those instructions.

The processor would fetch a new instruction whenever it needs to. The modern processors usually fetch multiple instructions in one clock cycle for better performance. However, the YARP processor would request for one instruction only whenever it has completely processed the last instruction i.e. after every clock cycle.

Design Requirements

In order to keep things simple, the memory returns data on the same cycle as the request. Since the YARP processor is single-cycle, this means that the instructions would be executed in one cycle and hence the processor can easily fetch a new instruction at the beginning of the next cycle.

Interface Definition

The instruction fetch would have the following interface definition:

• instr_mem_pc_i : This input represents the current Program Counter value
• instr_mem_req_o : Outgoing request to the instruction memory
• instr_mem_addr_o : Outgoing address from where the instruction should be fetched
• mem_rd_data_i : Icoming read data from the instruction memory
• instr_mem_instr_o : Outgoing instruction to the decode stage

Apart from the instr_mem_req_o signal all the other inputs and outputs would be 32-bit wide. The instr_mem_req_o is a single bit output.

Interface Requirement

• The instruction request must be asserted after YARP processor comes out of reset
• The instruction memory would respond back data on the same cycle which is why there's no ready signal associated with the interface