Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

# Yet Another RISC-V Processor (YARP)

The video in this lesson introduces you to the Yet Another RISC-V Processor (YARP) core. Building
on the previous lesson, this chapter would discuss the various building blocks of the RISC-V processor.

From next lesson onwards, we would start designing these blocks one-by-one and would look into the
hardware details for each of the blocks. The YARP core would consist of the following units:
- Instruction Fetch
- Instruction Decode
- Register File
- Instruction Execute
- Data Memory
- Control
- Branch Control
- Top

This lesson would give a nice introduction to the single cycle processor design. In the next lesson
we would start designing the Instruction Fetch unit for the YARP core.
